Datasheet
LPC Interface Bridge Registers (D31:F0)
302 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.3.8 SMI_STS—SMI Status Register
I/O Address: PMBASE + 34h Attribute: RO, R/WC
Default Value: 00000000h Size: 32 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Core
Note: If the corresponding _EN bit is set when the _STS bit is set, Intel® Xeon® Processor D-
1500 Product Family will cause an SMI# (except bits 8–10 and 12, which do not need
enable bits since they are logic ORs of other registers that have enable bits). Intel®
Xeon® Processor D-1500 Product Family uses the same GPE0_EN register (I/O
address: PMBase+2Ch) to enable/disable both SMI and ACPI SCI general purpose input
events. ACPI OS assumes that it owns the entire GPE0_EN register per the ACPI
specification. Problems arise when some of the general-purpose inputs are enabled as
SMI by BIOS, and some of the general purpose inputs are enabled for SCI. In this case
ACPI OS turns off the enabled bit for any GPIx input signals that are not indicated as
SCI general-purpose events at boot, and exit from sleeping states. BIOS should define
a dummy control method which prevents the ACPI OS from clearing the SMI GPE0_EN
bits.
1 End of SMI (EOS) — R/W (special). This bit controls the arbitration of the SMI signal to the
processor. This bit must be set for Intel® Xeon® Processor D-1500 Product Family to assert SMI#
low to the processor after SMI# has been asserted previously.
0 = Once Intel® Xeon® Processor D-1500 Product Family asserts SMI# low, the EOS bit is
automatically cleared.
1 = When this bit is set to 1, SMI# signal will be de-asserted for 4 PCI clocks before its assertion.
In the SMI handler, the processor should clear all pending SMIs (by servicing them and then
clearing their respective status bits), set the EOS bit, and exit SMM. This will allow the SMI
arbiter to re-assert SMI upon detection of an SMI event and the setting of a SMI status bit.
Note: Intel® Xeon® Processor D-1500 Product Family is able to generate 1st SMI after reset
even though EOS bit is not set. Subsequent SMI require EOS bit is set.
0 GBL_SMI_EN — R/W.
0 = No SMI# will be generated by Intel® Xeon® Processor D-1500 Product Family. This bit is reset
by a PCI reset event.
1 = Enables the generation of SMI# in the system upon any enabled SMI event.
Note: When the SMI_LOCK bit is set, this bit cannot be changed.
Bit Description
Bit Description
31:28 Reserved
27 GPIO_UNLOCK_SMI_STS — R/WC. This bit will be set if the GPIO registers lockdown logic is
requesting an SMI#. Writing a 1 to this bit position clears this bit to 0.
26 SPI_STS — RO. This bit will be set if the SPI logic is generating an SMI#. This bit is read only
because the sticky status and enable bits associated with this function are located in the SPI
registers.
25:22 Reserved
21 MONITOR_STS — RO. This bit will be set if the Trap/SMI logic has caused the SMI. This will occur
when the processor or a bus master accesses an assigned register (or a sequence of accesses). See
Section 5.1.16 through Section 5.1.32 for details on the specific cause of the SMI.
20 PCI_EXP_SMI_STS — RO. PCI Express* SMI event occurred. This could be due to a PCI Express*
PME event or Hot-Plug event.
19 Reserved
18 INTEL_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of the SMI status bits
in the Intel-Specific EHCI SMI Status Register ANDed with the corresponding enable bits. This bit will
not be active if the enable bits are not set. Writes to this bit will have no effect.
All integrated EHCIs are represented with this bit.
17 LEGACY_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of the SMI status
bits in the EHCI Legacy Support Register ANDed with the corresponding enable bits. This bit will not
be active if the enable bits are not set. Writes to this bit will have no effect.
All integrated ECHIs are represented with this bit.