Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 301
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
29:28 Reserved
27 GPIO_UNLOCK_SMI_EN— R/WO. Setting this bit will cause Intel® Xeon® Processor D-1500
Product Family to generate an SMI# when the GPIO_UNLOCK_SMI_STS bit is set in the SMI_STS
register.
Once written to 1, this bit can only be cleared by PLTRST#.
26:19 Reserved
18 INTEL_USB2_EN — R/W.
0 = Disable
1 = Enables Intel-Specific EHCI SMI logic to cause SMI#.
17 LEGACY_USB2_EN — R/W.
0 = Disable
1 = Enables legacy EHCI logic to cause SMI#.
16:15 Reserved
14 PERIODIC_EN — R/W.
0 = Disable.
1 = Enables Intel® Xeon® Processor D-1500 Product Family to generate an SMI# when the
PERIODIC_STS bit (PMBASE + 34h, bit 14) is set in the SMI_STS register (PMBASE + 34h).
13 TCO_EN — R/W.
0 = Disables TCO logic generating an SMI#. If the NMI2SMI_EN bit is set, SMIs that are caused by
re-routed NMIs will not be gated by the TCO_EN bit. Even if the TCO_EN bit is 0, NMIs will still
be routed to cause SMIs.
1 = Enables the TCO logic to generate SMI#.
Note: This bit cannot be written once the TCO_LOCK bit is set.
12 Reserved
11 MCSMI_EN Microcontroller SMI Enable (MCSMI_EN) — R/W.
0 = Disable.
1 = Enables Intel® Xeon® Processor D-1500 Product Family to trap accesses to the microcontroller
range (62h or 66h) and generate an SMI#. The “trapped’ cycles will be claimed by Intel®
Xeon® Processor D-1500 Product Family on PCI, but not forwarded to LPC.
10:8 Reserved
7 BIOS Release (BIOS_RLS) — WO.
0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.
1 = Enables the generation of an SCI interrupt for ACPI software when a one is written to this bit
position by BIOS software.
Note: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set. Software must take
great care not to set the BIOS_RLS bit (which causes GBL_STS to be set) if the SCI handler
is not in place.
6 Software SMI# Timer Enable (SWSMI_TMR_EN) — R/W.
0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the timer and the
SMI# will not be generated.
1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout period depends upon
the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set and an SMI# is generated.
SWSMI_TMR_EN stays set until cleared by software.
5 APMC_EN — R/W.
0 = Disable. Writes to the APM_CNT register will not cause an SMI#.
1 = Enables writes to the APM_CNT register to cause an SMI#.
4 SLP_SMI_EN — R/W.
0 = Disables the generation of SMI# on SLP_EN. This bit must be 0 before the software attempts to
transition the system into a sleep state by writing a 1 to the SLP_EN bit.
1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an SMI#, and the
system will not transition to the sleep state based on that write to the SLP_EN bit.
3 LEGACY_USB_EN — R/W.
0 = Disable.
1 = Enables legacy USB circuit to cause SMI#.
2
BIOS_EN — R/W.
0 = Disable.
1 = Enables the generation of SMI# when ACPI software writes a 1 to the GBL_RLS bit
(D31:F0:PMBase + 04h:bit 2). If the BIOS_STS bit (D31:F0:PMBase + 34h:bit 2), which gets
set when software writes 1 to GBL_RLS bit, is already a 1 at the time that BIOS_EN becomes 1,
an SMI# will be generated when BIOS_EN gets set.
Bit Description