Datasheet

LPC Interface Bridge Registers (D31:F0)
300 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.3.7 SMI_EN—SMI Control and Enable Register
I/O Address: PMBASE + 30h Attribute: R/W, R/WO, WO
Default Value: 00000002h Size: 32 bit
Lockable: No Usage: ACPI or Legacy
Power Well: Core
Note: This register is symmetrical to the SMI status register.
31:16 GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to cause a
SCI, and/or wake event. These bits are cleared by RSMRST#.
Note: Mapping is as follows: bit 31 corresponds to GPI15... and bit 16 corresponds to GPI0.
15:14 Reserved
13 PME_B0_EN — R/W.
0 = Disable
Note: Enables the setting of the PME_B0_STS bit to generate a wake event and/or an SCI or
SMI#.
12 Reserved
11 PME_EN — R/W.
0 = Disable.
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI. PME# can be
a wake event from the S1–S4 state or from S5 (if entered using SLP_EN, but not power
button override).
10 Reserved
9 PCI_EXP_EN — R/W.
0 = Disable SCI generation upon PCI_EXP_STS bit being set.
1 = Enables Intel® Xeon® Processor D-1500 Product Family to cause an SCI when
PCI_EXP_STS bit is set. This is used to allow the PCI Express* ports, including the link to
the processor, to cause an SCI due to wake/PME events.
8 RI_EN — R/W. The value of this bit will be maintained through a G3 state and is not affected by
a hard reset caused by a CF9h write.
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake event.
7 Reserved
6 TCOSCI_EN — R/W.
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
5:3 Reserved
2 SWGPE_EN— R/W. This bit allows software to control the assertion of SWGPE_STS bit. This bit
This bit, when set to 1, enables the SW GPE function. If SWGPE_CTRL is written to a 1, hardware
will set SWGPE_STS (acts as a level input)
If SWGPE_STS, SWGPE_EN, and SCI_EN are all 1s, an SCI will be generated
If SWGPE_STS = 1, SWGPE_EN = 1, SCI_EN = 0, and GBL_SMI_EN = 1 then an SMI# will be
generated
1 HOT_PLUG_EN — R/W.
0 = Disables SCI generation upon the HOT_PLUG_STS bit being set.
1 = Enables Intel® Xeon® Processor D-1500 Product Family to cause an SCI when the
HOT_PLUG_STS bit is set. This is used to allow the PCI Express* ports to cause an SCI due
to Hot-Plug events.
0 Reserved
Bit Description
Bit Description
31 xHCI SMI Enable (xHCI _SMI_EN) — R/W.
0 = Disable
1 = Enables xHCI to generate an SMI#
30 ME SMI Enable (ME _SMI_EN) — R/W.
0 = Disable
1 = Enables ME to generate an SMI#