Datasheet

Intel® Xeon® Processor D-1500 Product Family 3
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Content
1 Introduction.....................................................................................................................24
1.1 About This Manual ....................................................................................................24
1.1.1 Chapter Descriptions .....................................................................................25
1.2 Overview .................................................................................................................26
1.2.1 Capability Overview.......................................................................................27
1.3 Intel® Xeon® Processor D-1500 Product Family Integrated Chipset Definition ..................32
1.4 Device and Revision ID Table .....................................................................................32
2 Intel® Xeon® Processor D-1500 Product Family and System Clocks................................35
2.1 Straps Related to Clock Configuration ..........................................................................35
2.2 SoC Clocking Requirements........................................................................................35
2.3 Functional Blocks ......................................................................................................37
2.4 Clock Configuration Access Overview ...........................................................................37
2.5 Integrated Clock Controller (ICC) Registers ..................................................................38
2.5.1 ICC Registers under Intel
®
Management Engine (Intel
®
ME) Control ....................38
3 Functional Description .....................................................................................................49
3.1 PCI-to-PCI Bridge .....................................................................................................49
3.1.1 PCI Legacy Mode...........................................................................................49
3.2 PCI Express* Root Ports (D28:F0~F7) .........................................................................49
3.2.1 Supported PCIe* Port Configurations ...............................................................50
3.2.2 Interrupt Generation......................................................................................50
3.2.3 Power Management .......................................................................................51
3.2.4 SERR# Generation ........................................................................................52
3.2.5 Hot-Plug ......................................................................................................53
3.3 Gigabit Ethernet Controller (B0:D25:F0) ......................................................................55
3.3.1 GbE PCI Express* Bus Interface ......................................................................56
3.3.2 Error Events and Error Reporting.....................................................................57
3.3.3 Ethernet Interface .........................................................................................58
3.3.4 PCI Power Management .................................................................................58
3.3.5 Configurable LEDs .........................................................................................60
3.3.6 Function Level Reset Support (FLR) .................................................................61
3.4 Low Pin Count (LPC) Bridge (with System and Management Functions) (D31:F0)...............62
3.4.1 LPC Interface................................................................................................62
3.5 DMA Operation (D31:F0) ...........................................................................................67
3.5.1 Channel Priority ............................................................................................68
3.5.2 Address Compatibility Mode ............................................................................68
3.5.3 Summary of DMA Transfer Sizes .....................................................................69
3.5.4 Autoinitialize.................................................................................................69
3.5.5 Software Commands......................................................................................70
3.6 Low Pin Count (LPC) DMA ..........................................................................................70
3.6.1 Asserting DMA Requests.................................................................................70
3.6.2 Abandoning DMA Requests .............................................................................71
3.6.3 General Flow of DMA Transfers........................................................................71
3.6.4 Terminal Count .............................................................................................72
3.6.5 Verify Mode ..................................................................................................72
3.6.6 DMA Request De-assertion .............................................................................72
3.6.7 SYNC Field / LDRQ# Rules..............................................................................73
3.7 8254 Timers (D31:F0) ...............................................................................................74
3.7.1 Timer Programming.......................................................................................74
3.7.2 Reading from the Interval Timer......................................................................75
3.8 8259 Programmable Interrupt Controllers (PIC) (D31:F0)...............................................77
3.8.1 Interrupt Handling.........................................................................................78
3.8.2 Initialization Command Words (ICWx)..............................................................79
3.8.3 Operation Command Words (OCW)..................................................................80
3.8.4 Modes of Operation .......................................................................................80
3.8.5 Masking Interrupts ........................................................................................82
3.8.6 Steering PCI Interrupts ..................................................................................83
3.9 Advanced Programmable Interrupt Controller (APIC) (D31:F0)........................................83
3.9.1 Interrupt Handling.........................................................................................83
3.9.2 Interrupt Mapping .........................................................................................84
3.9.3 PCI / PCI Express* Message-Based Interrupts...................................................85
3.9.4 IOxAPIC Address Remapping ..........................................................................85
3.9.5 External Interrupt Controller Support ...............................................................85