Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 299
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.3.6 GPE0_EN—General Purpose Event 0 Enables Register
I/O Address: PMBASE + 28h Attribute: R/W
Default Value: 0000000000000000h Size: 64-bit
Lockable: No Usage: ACPI
Power Well: Bits 0–7, 9, 12, 14–34, 36–63 Suspend,
Bits 8, 10–11, 13, 35 RTC
This register is symmetrical to the General Purpose Event 0 Status Register.
7 SMBus Wake Status (SMB_WAK_STS) — R/WC. Software clears this bit by writing a 1 to it.
0 = Wake event not caused by Intel® Xeon® Processor D-1500 Product Family’s SMBus logic.
1 = Set by hardware to indicate that the wake event was caused by Intel® Xeon® Processor D-
1500 Product Family’s SMBus logic. The SMI handler should then clear this bit.
NOTES:
1. The SMBus controller will independently cause an SMI# so this bit does not need to do so
(unlike the other bits in this register).
2. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is in
the S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep states,
software must clear this bit after each reception of the Wake/SMI# command or just prior to
entering the sleep state.
3. The SMBALERT_STS bit (SMB_BASE+00h:Bit 5) should be cleared by software before the
SMB_WAK_STS bit is cleared.
6 TCOSCI_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = TOC logic or thermal sensor logic did Not cause SCI.
1 = Set by hardware when the TCO logic or thermal sensor logic causes an SCI.
5:3 Reserved
2 SWGPE_STS — R/WC.
The SWGPE_CTRL bit (bit 1 of GPE_CTRL reg) acts as a level input to this bit.
1 HOT_PLUG_STS — R/WC.
0 = This bit is cleared by writing a 1 to this bit position.
1 = When a PCI Express* Hot-Plug event occurs. This will cause an SCI if the HOT_PLUG_EN and
SCI_EN bits are set.
0 Reserved
Bit Description
Bit Description
63 GPI[60]_EN - R/W. Refer to bit 56 for description.
62 GPI[57]_EN - R/W. Refer to bit 56 for description.
61 GPI[56]_EN - R/W. Refer to bit 56 for description.
60 GPI[43]_EN - R/W. Refer to bit 56 for description.
59 GPI[22]_EN - R/W. Refer to bit 56 for description.
58 GPI[21]_EN - R/W. Refer to bit 56 for description.
57 GPI[19]_EN - R/W. Refer to bit 56 for description.
56 GPI[17]_EN - R/W. This bit enables the corresponding GPI[n]_STS bits being set to cause an SCI
and/or wake event.
55:39 Reserved
38 WADT_EN - R/W. Used to enable the setting of the WADT_STS bit to generate wake/SMI#/SCI.
37-36 Reserved
35 GPI27_EN — R/W.
0 = Disable.
1 = Enable the setting of the GPI27_STS bit to generate a wake event/SCI/SMI#.
Note: Host wake events from the PHY through GPIO27 cannot be disabled by clearing this bit.
34:32 Reserved