Datasheet

LPC Interface Bridge Registers (D31:F0)
298 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
31:16 GPIn_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set). If the
corresponding enable bit is set in the GPE0_EN register, then when the GPI[n]_STS bit is set:
• If the system is in an S1–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused
depending on the GPI_ROUT bits (D31:F0:B8h, bits 31:30) for the corresponding GPI.
Note: Mapping is as follows: bit 31 corresponds to GPI[15]... and bit 16 corresponds to GPI[0].
GPIO[13] is not supported.
15:14 Reserved
13 PME_B0_STS — R/WC. This bit will be set to 1 by Intel® Xeon® Processor D-1500 Product
Family when any internal device with PCI Power Management capabilities on bus 0 asserts the
equivalent of the PME# signal. Additionally, if the PME_B0_EN bit and SCI_EN bits are set, and the
system is in an S0 state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if
SCI_EN is not set). If the PME_B0_EN bit is set, and the system is in an S1–S4 state (or S5 state
due to SLP_TYP and SLP_EN), then the setting of the PME_B0_STS bit will generate a wake event.
If the system is in an S5 state due to power button override, then the PME_B0_STS bit will not
cause a wake event or SCI.
The default for this bit is 0. Writing a 1 to this bit position clears this bit.
The following are internal devices which can set this bit:
• Intel Management Engine “maskable” wake events
•Integrated LAN
•SATA
•EHCI
12 Reserved
11 PME_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN and SCI_EN
bits are set, and the system is in an S0 state, then the setting of the PME_STS bit will
generate an SCI or SMI# (if SCI_EN is not set). If the PME_EN bit is set, and the system is in
an S1–S4 state (or S5 state due to setting SLP_TYP and SLP_EN), then the setting of the
PME_STS bit will generate a wake event. If the system is in an S5 state due to power button
override or a power failure, then PME_STS will not cause a wake event or SCI.
10 Reserved
9 PCI_EXP_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware to indicate that:
— The PME event message was received on one or more of the PCI Express* ports
— An Assert PMEGPE message received from the processor.
Notes:
1. The PCI WAKE# pin has no impact on this bit.
2. If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert
PMEGPE message must be received prior to the software write in order for the bit to be
cleared.
3. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the level-triggered SCI
will remain active.
4. A race condition exists where the PCI Express device sends another PME message because
the PCI Express device was not serviced within the time when it must resend the message.
This may result in a spurious interrupt, and this is comprehended and approved by the PCI
Express* Specification, Revision 1.0a. The window for this race condition is approximately
95–105 milliseconds.
8 RI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RI# input signal goes active.
Bit Description