Datasheet
LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 297
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.3.5 GPE0_STS—General Purpose Event 0 Status Register
I/O Address: PMBASE + 20h Attribute: Bits 0:32,35 R/WC
Bits 33:34, 36:63 RO
Default Value: 0000000000000000h Size: 64-bit
Lockable: No Usage: ACPI
Power Well: Bits 0–34, 36-37, 56–63: Suspend,
Bit 35, 38: Suspend
This register is symmetrical to the General Purpose Event 0 Enable Register. Unless
indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit
get set, Intel® Xeon® Processor D-1500 Product Family will generate a Wake Event.
Once back in an S0 state (or if already in an S0 state when the event occurs), Intel®
Xeon® Processor D-1500 Product Family will also generate an SCI if the SCI_EN bit is
set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set. Bits 31:16 are reset
by a CF9h full reset; bits 63:32 and 15:0 are not. All bits (except bit 35) are reset by
RSMRST#. Bit 35 is reset by DPWROK.
23:0 Timer Value (TMR_VAL) — RO. Returns the running count of the PM timer. This counter runs off a
3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0 during a PCI reset, and then
continues counting as long as the system is in the S0 state. After an S1 state, the counter will not be
reset (it will continue counting from the last value in S0 state.
Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the TMROF_STS bit
(PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur every 2.3435 seconds. If the
TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI interrupt is also generated.
Bit Description
Bit Description
63 GPI60_STS - R/WC. Refer to bit[56] in this register for description.
62 GPI57_STS - R/WC. Refer to bit[56] in this register for description.
61 Reserved
60 GPI43_STS - R/WC. Refer to bit[56] in this register for description.
59 GPI22_STS - R/WC. Refer to bit[56] in this register for description.
58 GPI21_STS - R/WC. Refer to bit[56] in this register for description.
57 GPI19_STS - R/WC. Refer to bit[56] in this register for description.
56 GPI17_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set). If the
corresponding enable bit is set in the GPE0_EN register, then when the GPI[n]_STS bit is set:
• If the system is in an S1–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused
depending on the GPI_ROUT2 bits (D31:F0:BCh, bits 15:0) for the corresponding GPI.
55-39 Reserved
38 Wake Alarm Device Timer Status (WADT_STS) — R/WC. This bit is set whenever any of the wake
alarm device timers signal a timer expiration.
37:36 Reserved
35 GPI27_STS — R/WC.
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a resume well reset.
This bit is set whenever GPIO27 is seen asserted low. GPIO27 is always monitored as an
input for the purpose of setting this bit, regardless of the actual GPIO configuration.
34:32 Reserved