Datasheet
LPC Interface Bridge Registers (D31:F0)
296 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.3.3 PM1_CNT—Power Management 1 Control Register
I/O Address: PMBASE + 04h
Attribute: R/W, WO
Default Value: 00000000h Size: 32 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Bits 0–9, 13-31: Core,
Bits 10–12: RTC
7.8.3.4 PM1_TMR—Power Management 1 Timer Register
I/O Address: PMBASE + 08h Attribute: RO
Default Value: 00000000h Size: 32 bits
Lockable: No Usage: ACPI
Power Well: Core
Bit Description
31:14 Reserved
13 Sleep Enable (SLP_EN) — WO. Setting this bit causes the system to sequence into the Sleep
state defined by the SLP_TYP field.
12:10 Sleep Type (SLP_TYP) — R/W. This 3-bit field defines the type of Sleep the system should
enter when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#.
9:3 Reserved
2 Global Release (GBL_RLS) — WO.
0 = This bit always reads as 0.
1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software has a
corresponding enable and status bits to control its ability to receive ACPI events.
1 Bus Master Reload (BM_RLD) — R/W. This bit is treated as a scratchpad bit. This bit is reset to
0 by PLTRST#
0 = Bus master requests will not cause a break from the C3 state.
1 = Enables Bus Master requests (internal or external) to cause a break from the C3 state.
If software fails to set this bit before going to C3 state, Intel® Xeon® Processor D-1500 Product
Family will still return to a snoopable state from C3 or C4 states due to bus master activity.
0 SCI Enable (SCI_EN) — R/W. Selects the SCI interrupt or the SMI# interrupt for various events
including the bits in the PM1_STS register (bit 10, 8, 0), and bits in GPE0_STS.
0 = These events will generate an SMI#.
1 = These events will generate an SCI.
Code Master Interrupt
000b ON: Typically maps to S0 state.
001b Puts Processor Core in S1 state.
010b Reserved
011b Reserved
100b Reserved
101b Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state.
110b Suspend-To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps to S4 state.
111b Soft Off. Assert SLP_S3#, SLP_S4#, and SLP_S5#: Typically maps to S5 state.
Bit Description
31:24 Reserved