Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 295
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.3.2 PM1_EN—Power Management 1 Enable Register
I/O Address: PMBASE + 02h Attribute: R/W
Default Value: 0000h Size: 16 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Bits 0–7: Core,
Bits 8–9, 11–13, 15: Suspend,
Bit 14: Suspend,
Bit 10: RTC
4 Bus Master Status (BM_STS) — R/WC. This bit will not cause a wake event, SCI or SMI#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by Intel® Xeon® Processor D-1500 Product Family when a Intel® Xeon® Processor D-1500
Product Family-visible bus master requests access to memory or the BMBUSY# signal is active.
3:1 Reserved
0 Timer Overflow Status (TMROF_STS) — R/WC.
0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.
1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23).
This will occur every 2.3435 seconds. When the TMROF_EN bit (PMBASE + 02h, bit 0) is set,
then the setting of the TMROF_STS bit will additionally generate an SCI or SMI# (depending on
the SCI_EN).
Bit Description
Bit Description
15 Reserved
14 PCI Express* Wake Disable(PCIEXPWAK_DIS) — R/W. Modification of this bit has no impact on
the value of the PCIEXP_WAKE_STS bit.
0 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register enabled to wake the system.
1 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register disabled from waking the
system.
13:11 Reserved
10 RTC Event Enable (RTC_EN) — R/W. This bit is in the RTC well to allow an RTC event to wake after
a power failure.
0 = No SCI (or SMI#) or wake event is generated then RTC_STS (PMBASE + 00h, bit 10) goes
active.
1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit goes active.
9 Reserved
8 Power Button Enable (PWRBTN_EN) — R/W. This bit is used to enable the setting of the
PWRBTN_STS bit to generate a power management event (SMI#, SCI). PWRBTN_EN has no effect
on the PWRBTN_STS bit (PMBASE + 00h, bit 8) being set by the assertion of the power button. The
Power Button is always enabled as a Wake event.
0 = Disable.
1 = Enable.
7:6 Reserved
5 Global Enable (GBL_EN) — R/W. When both the GBL_EN and the GBL_STS bit (PMBASE + 00h, bit
5) are set, an SCI is raised.
0 = Disable.
1 = Enable SCI on GBL_STS going active.
4:1 Reserved
0 Timer Overflow Interrupt Enable (TMROF_EN) — R/W. Works in conjunction with the SCI_EN
bit (PMBASE + 04h, bit 0) as described below:
TMROF_EN SCI_EN Effect when TMROF_STS is set
0 X No SMI# or SCI
10 SMI#
11 SCI