Datasheet

LPC Interface Bridge Registers (D31:F0)
294 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Bit Description
15 Wake Status (WAK_STS) — R/WC. This bit is not affected by hard resets caused by a CF9 write,
but is reset by RSMRST#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the system is in one of the sleep states (using the SLP_EN bit) and an
enabled wake event occurs. Upon setting this bit, Intel® Xeon® Processor D-1500 Product
Family will transition the system to the ON state.
If the AFTERG3_EN bit is not set and a power failure (such as removed batteries) occurs without the
SLP_EN bit set, the system will return to an S0 state when power returns, and the WAK_STS bit will
not be set.
If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit having been set, the
system will go into an S5 state when power returns, and a subsequent wake event will cause the
WAK_STS bit to be set. Any subsequent wake event would have to be caused by either a Power
Button press, or an enabled wake event that was preserved through the power failure (enable bit in
the RTC well).
14 PCI Express* Wake Status (PCIEXPWAK_STS) — R/WC.
0 = Software clears this bit by writing a 1 to it. If the WAKE# pin is still active during the write or
the PME message received indication has not been cleared in the root port, then the bit will
remain active (that is, all inputs to this bit are level-sensitive).
1 = This bit is set by hardware to indicate that the system woke due to a PCI Express wakeup event.
This wakeup event can be caused by the PCI Express WAKE# pin being active or receipt of a PCI
Express PME message at a root port. This bit is set only when one of these events causes the
system to transition from a non-S0 system power state to the S0 system power state. This bit is
set independent of the state of the PCIEXP_WAKE_DIS bit.
Note: This bit does not itself cause a wake event or prevent entry to a sleeping state. Thus, if the
bit is 1 and the system is put into a sleeping state, the system will not automatically wake.
13:12 Reserved
11 Power Button Override Status (PWRBTNOR_STS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a Power Button Override occurs (that is, the power button is pressed for
at least 4 consecutive seconds), due to the corresponding bit in the SMBus slave message, Intel
ME Initiated Power Button Override, Intel ME Initiated Host Reset with Power down or due to an
internal thermal sensor catastrophic condition. The power button override causes an
unconditional transition to the S5 state. The BIOS or SCI handler clears this bit by writing a 1 to
it. This bit is not affected by hard resets using CF9h writes, and is not reset by RSMRST#. Thus,
this bit is preserved through power failures. If this bit is still asserted when the global SCI_EN is
set, an SCI will be generated.
10 RTC Status (RTC_STS) — R/WC. This bit is not affected by hard resets caused by a CF9 write, but
is reset by DPWROK.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8# signal). Additionally
if the RTC_EN bit (PMBASE + 02h, bit 10) is set, the setting of the RTC_STS bit will generate a
wake event.
9Reserved
8 Power Button Status (PWRBTN__STS) — R/WC. This bit is not affected by hard resets caused by
a CF9 write but is reset by DPWROK.
0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears the
PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to the S5 state with
only PWRBTN# enabled as a wake event.
This bit can be cleared by software by writing a one to the bit position.
1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent of any other
enable bit.
In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or SMI# if SCI_EN
is not set) will be generated.
In any sleeping state S1–S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and PWRBTN_STS are
both set, a wake event is generated.
Note: If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is sell asserted,
this will not cause the PWRBN_STS bit to be set. The PWRBTN# signal must go inactive and
active again to set the PWRBTN_STS bit.
7:6 Reserved
5 Global Status (GBL _STS) — R/WC.
0 = The SCI handler should then clear this bit by writing a 1 to the bit location.
1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI handler. BIOS has a
corresponding bit, BIOS_RLS, which will cause an SCI and set this bit.