Datasheet
LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 293
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.3 Power Management I/O Registers
Ta b l e 7- 1 1 shows the registers associated with ACPI and Legacy power management
support. These registers locations are all offsets from the ACPI base address defined in
the PCI Device 31: Function 0 space (PMBASE), and can be moved to any 128-byte
aligned I/O location. In order to access these registers, the ACPI Enable bit (ACPI_EN)
must be set. The registers are defined to support the ACPI 4.0a specification and
generally use the same bit names.
Note: All reserved bits and registers will always return 0 when read, and will have no effect
when written.
7.8.3.1 PM1_STS—Power Management 1 Status Register
I/O Address: PMBASE + 00h Attribute: R/WC
Default Value: 0000h Size: 16 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Bits 0–7: Core,
Bits 12-15: Suspend
Bit 11: RTC,
Bits 8, 10 and 14: Suspend
If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN
register, then Intel® Xeon® Processor D-1500 Product Family will generate a Wake
Event. Once back in an S0 state (or if already in an S0 state when the event occurs),
Intel® Xeon® Processor D-1500 Product Family will also generate an SCI if the SCI_EN
bit is set, or an SMI# if the SCI_EN bit is not set.
Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but
can cause an SMI# or SCI.
Table 7-11. ACPI and Legacy I/O Register Map
PMBASE
+ Offset
Mnemonic Register Name Default Attribute
00h–01h PM1_STS PM1 Status 0000h R/WC
02h–03h PM1_EN PM1 Enable 0000h R/W
04h–07h PM1_CNT PM1 Control 00000000h R/W, WO
08h–0Bh PM1_TMR PM1 Timer 00000000h RO
20h–27h GPE0_STS General Purpose Event 0 Status 000000000000
0000h
RO, R/WC
28h–2Fh GPE0_EN General Purpose Event 0 Enables 00000000
00000000h
RO, R/W
30h–33h SMI_EN SMI# Control and Enable 00000002h R/W, WO,
R/WO
34h–37h SMI_STS SMI Status 00000000h R/WC, RO
38h–39h ALT_GPI_SMI_EN Alternate GPI SMI Enable 0000h R/W
3Ah–3Bh ALT_GPI_SMI_STS Alternate GPI SMI Status 0000h R/WC
42h GPE_CNTL General Purpose Event Control 00h R/W
44h–45h DEVACT_STS Device Activity Status 0000h R/WC
50h PM2_CNT PM2 Control 00h R/W
5Ch–5Dh ALT_GPI_SMI_EN2 Alternate GPI SMI Enable 2 Register 0000h R/W, RO
5Eh–5Fh ALT_GPI_SMI_STS2 Alternate GPI SMI Status 2 Register 0000h RO, RWC
60h–7Fh — Reserved for TCO — —