Datasheet

LPC Interface Bridge Registers (D31:F0)
292 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: If the GPIO is not set to an input, or if the Native function is selected, then the corresponding field in
this register has no effect.
7.8.2 APM I/O Decode Register
Tab l e 7- 1 0 shows the I/O registers associated with APM support. This register space is
enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved
(fixed I/O location).
7.8.2.1 APM_CNT—Advanced Power Management Control Port Register
I/O Address: B2h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Usage: Legacy Only
Power Well: Core
7.8.2.2 APM_STS—Advanced Power Management Status Port Register
I/O Address: B3h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Usage: Legacy Only
Power Well: Core
7:6 GPI22 Route — R/W. See bits 1:0 for description.
5:4 GPI21 Route — R/W. See bits 1:0 for description.
3:2 GPI19 Route — R/W. See bits 1:0 for description.
1:0 GPI17 Route — R/W. If the corresponding GPIO is implemented and is configured as an Input, then
a ‘1’ in the corresponding GP_LVL bit can be routed to cause an interrupt. The type of interrupt (that
is, NMI, SMI# or SCI) depends on the configuration bits in this register as well as the configuration
bits in related registers, as described below.
00 = No effect.
01 = SMI# (if corresponding ALT_GPI_SMI_EN2 bit is also set).
10 = SCI (if corresponding GPE0_EN bit is also set).
11 = NMI (if corresponding GPI_NMI_EN is also set).
If the system is in an S4-S5 state and if the GPE0_EN bit is also set, then the GPIO can cause a Wake
event from Sx state, even if the GPIO is NOT routed to cause an NMI, SMI# or SCI. Exception: If the
system is in S5 state due to a power button override, then the GPIs will not cause wake events.
Further, Core well GPIs are not capable of waking the system from sleep states where the Core well
is not powered.
Bit Description
Table 7-10. APM Register Map
Address Mnemonic Register Name Default Type
B2h APM_CNT Advanced Power Management Control Port 00h R/W
B3h APM_STS Advanced Power Management Status Port 00h R/W
Bit Description
7:0 Used to pass an APM command between the OS and the SMI handler. Writes to this port not only
store data in the APMC register, but also generates an SMI# when the APMC_EN bit is set.
Bit Description
7:0 Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad register and is
not affected by any other register or function (other than a PCI reset).