Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 291
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.1.8 GPI_ROUT—GPI Routing Control Register (PM—D31:F0)
Offset Address: B8h–BBh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: No Power Well: Suspend
Note: If the GPIO is not set to an input, or if the Native function is selected, then the corresponding field in
this register has no effect.
7.8.1.9 GPI_ROUT2—GPI Routing Control Register #2 (PM-D31:F0)
Offset Address: BCh–BFh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: No Power Well: Suspend
1:0 Reserved
Bit Description
Bit Description
31:30 GPI 15 Route — R/W. See bits 1:0 for description.
29:28 GPI 14 Route — R/W. See bits 1:0 for description.
27:26 Reserved
25:24 GPI 12 Route — R/W. See bits 1:0 for description.
23:22 GPI 11 Route — R/W. See bits 1:0 for description.
21:20 GPI 10 Route — R/W. See bits 1:0 for description.
19:18 GPI 9 Route — R/W. See bits 1:0 for description.
17:16 GPI 8 Route — R/W. See bits 1:0 for description.
15:14 GPI 7 Route — R/W. See bits 1:0 for description.
13:12 GPI 6 Route — R/W. See bits 1:0 for description.
11:10 GPI 5 Route — R/W. See bits 1:0 for description.
9:8 GPI 4 Route — R/W. See bits 1:0 for description.
7:6 GPI 3 Route — R/W. See bits 1:0 for description.
5:4 GPI 2 Route — R/W. See bits 1:0 for description.
3:2 GPI 1 Route — R/W. See bits 1:0 for description.
1:0 GPI 0 Route — R/W. If the corresponding GPIO is implemented and is configured as an Input, then
a ‘1’ in the corresponding GP_LVL bit can be routed to cause an interrupt. The type of interrupt (that
is, NMI, SMI# or SCI) depends on the configuration bits in this register as well as the configuration
bits in related registers, as described below.
00 = No effect.
01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set).
10 = SCI (if corresponding GPE0_EN bit is also set).
11 = NMI (if corresponding GPI_NMI_EN is also set).
If the system is in an S4–S5 state and if the GPE0_EN bit is also set, then the GPIO can cause a
Wake event from Sx state, even if the GPIO is NOT routed to cause an NMI, SMI#, or SCI. Exception:
If the system is in S5 state due to a power button override, then the GPIs will not cause wake
events. Further, Core well GPIs are not capable of waking the system from sleep states where the
Core well is not powered.
Bit Description
31:16 Reserved
15:14 GPI60 Route — R/W. See bits 1:0 for description.
13:12 GPI57 Route — R/W. See bits 1:0 for description.
11:10 Reserved
9:8 GPI43 Route — R/W. See bits 1:0 for description.