Datasheet
LPC Interface Bridge Registers (D31:F0)
290 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.1.5 CIR4—Chipset Initialization Register 4 (PM—D31:F0)
Offset Address: A9h Attribute: R/W
Default Value: 03h Size: 8 bits
Lockable: No Usage: ACPI, Legacy
Power Well: Core
7.8.1.6 BM_BREAK_EN_2 Register #2 (PM—D31:F0)
Offset Address: AAh Attribute: R/W, RO
Default Value: 00h Size: 8 bits
Lockable: No Usage: ACPI, Legacy
Power Well: Core
7.8.1.7 BM_BREAK_EN Register (PM—D31:F0)
Offset Address: ABh Attribute: R/W, RO
Default Value: 00h Size: 8 bits
Lockable: No Usage: ACPI, Legacy
Power Well: Core
2 SLP Stretching Policy Lock-Down (SLP_STR_POL_LOCK) — R/WLO. When set to 1, this bit
locks down the Disable SLP Stretching After SUS Well Power Up, SLP_S3# Minimum Assertion
Width, SLP_S4# Minimum Assertion Width, SLP_S4# Assertion Stretch Enable bits in the
GEN_PMCON_3 register, making them read-only.
This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are always
ignored.
This bit is cleared by platform reset.
1 ACPI_BASE_LOCK — R/WLO. When set to 1, this bit locks down the ACPI Base Address
Register (ABASE) at offset 40h. The Base Address Field becomes read-only.
This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are always
ignored. Once locked by writing 1, the only way to clear this bit is to perform a platform reset.
0 Reserved
Bit Description
Bit Description
7:0 CIR4 Field 1 — R/W. BIOS may program this register.
Bit Description
7:2 Reserved
1 xHCI Break Enable (xHCI_BREAK_EN) — R/W.
0 = xHCI traffic will not cause BM_STS to be set.
1 = xHCI traffic will cause BM_STS to be set.
0 SATA3 Break Enable (SATA3_BREAK_EN) — R/W.
0 = SATA3 traffic will not cause BM_STS to be set.
1 = SATA3 traffic will cause BM_STS to be set.
Bit Description
7 Storage Break Enable (STORAGE_BREAK_EN) — R/W.
0 = Serial ATA traffic will not cause BM_STS to be set.
1 = Serial ATA traffic will cause BM_STS to be set.
6 PCIE_BREAK_EN — R/W.
0 = PCI Express* traffic will not cause BM_STS to be set.
1 = PCI Express traffic will cause BM_STS to be set.
5:3 Reserved
2 EHCI_BREAK_EN — R/W.
0 = EHCI traffic will not cause BM_STS to be set.
1 = EHCI traffic will cause BM_STS to be set.