Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 289
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC clock period
may not be detected by Intel® Xeon® Processor D-1500 Product Family.
7.8.1.4 GEN_PMCON_LOCK—General Power Management Configuration Lock
Register
Offset Address: A6h Attribute: RO, R/WLO
Default Value: 00h Size: 8 bits
Lockable: No Usage: ACPI
Power Well: Core
5:4 SLP_S4# Minimum Assertion Width(SLP_S4_MIN_ASST_WDTH)— R/WL. This field
indicates the minimum assertion width of the SLP_S4# signal to ensure that the DRAM modules
have been safely power-cycled.
Valid values are:
11 = 1 second
10 = 2 seconds
01 = 3 seconds
00 = 4 seconds
This value is used in two ways:
1. If the SLP_S4# assertion width is ever shorter than this time, a status bit is set for BIOS to
read when S0 is entered.
2. If enabled by bit 3 in this register, the hardware will prevent the SLP_S4# signal from de-
asserting within this minimum time period after asserting.
RTCRST# forces this field to the conservative default state (00b).
Notes:
1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.
2. The logic that measures this time is in the suspend power well. Therefore, when leaving a
G3 state, the minimum time is measured from the de-assertion of the internal suspend
well reset (unless the “Disable SLP Stretching After SUS Well Power Up” bit is set).
3 SLP_S4# Assertion Stretch Enable — R/WL.
0 = The SLP_S4# minimum assertion time is defined in Power Sequencing and Reset Signal
Timings table.
1 = The SLP_S4# signal minimally assert for the time specified in bits 5:4 of this register.
This bit is cleared by RTCRST#.
Note: This bit is RO when the SLP Stretching Policy Lock-Down bit is set.
2 RTC Power Status (RTC_PWR_STS) — R/W. This bit is set when RTCRST# indicates a weak
or missing battery. The bit is not cleared by any type of reset. The bit will remain set until the
software clears it by writing a 0 back to this bit position.
1 Power Failure (PWR_FLR) — R/WC. This bit is in the DeepSx well and defaults to 1 based on
DPWROK de-assertion (not cleared by any type of reset).
0 = Indicates that the trickle current has not failed since the last time the bit was cleared.
Software clears this bit by writing a 1 to it.
1 = Indicates that the trickle current (from the main battery or trickle supply) was removed or
failed.
Note: Clearing CMOS in a Intel® Xeon® Processor D-1500 Product Family-based platform
can be done by using a jumper on RTCRST# or GPI. Implementations should not
attempt to clear CMOS by using a jumper to pull VccRTC low.
0 AFTERG3_EN — R/W. This bit determines what state to go to when power is re-applied after a
power failure (G3 state). This bit is in the RTC well and is only cleared by RTCRST# assertion.
0 = System will return to S0 state (boot) after power is re-applied.
1 = System will return to the S5 state (except if it was in S4, in which case it will return to S4).
In the S5 state, the only enabled wake event is the Power Button or any enabled wake
event that was preserved through the power failure.
Bit Description
Bit Description
7:3 Reserved