Datasheet
LPC Interface Bridge Registers (D31:F0)
288 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
12 Disable SLP Stretching After SUS Well Power Up (DIS_SLP_STRCH_SUS_UP): R/WL
0 = Enables stretching on SLP signals after SUS power failure as enabled and configured in
other fields.
1 = Disables stretching on SLP signals when powering up after a SUS well power loss.
regardless of the state of the SLP_S4# Assertion Stretch Enable (bit 3).
This bit is cleared by the RTCRST# pin.
Notes:
1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.
2. If this bit is cleared, SLP stretch timers start on SUS well power up (Intel® Xeon®
Processor D-1500 Product Family has no ability to count stretch time while the SUS well is
powered down).
3. This policy bit has a different effect on SLP_SUS# stretching than on the other SLP_* pins
since SLP_SUS# is the control signal for one of the scenarios where SUS well power is
lost the effect of setting this bit to '1' on:
— SLP_S3# and SLP_S4# stretching: disabled after any SUS power loss.
— SLP_SUS# stretching: disabled after G3,
11:10 SLP_S3# Minimum Assertion Width (SLP_S3_MIN_ASST_WDTH): R/WL This 2-bit value
indicates the minimum assertion width of the SLP_S3# signal to ensure that the Main power
supplies have been fully power-cycled.
Valid Settings are:
00 = 60 us
01 = 1 ms
10 = 50 ms
11 = 2 s
This bit is cleared by the RSMRST# pin.
Note: This field is RO when the SLP Stretching Policy Lock-Down bit is set.
9 General Reset Status (GEN_RST_STS) — R/WC. This bit is set by hardware whenever
PLTRST# asserts for any reason other than going into a software-entered sleep state (using
PM1CNT.SLP_EN write) or a suspend well power failure (RSMRST# pin assertion). BIOS is
expected to consult and then write a 1 to clear this bit during the boot flow before determining
what action to take based on PM1_STS.WAK_STS = 1. If GEN_RST_STS = 1, the cold reset
boot path should be followed rather than the resume path, regardless of the setting of
WAK_STS.
This bit is cleared by the RSMRST# pin.
8 Reserved.
7:6 SWSMI_RATE_SEL — R/W. This field indicates when the SWSMI timer will time out.
Valid values are:
00 = 1.5 ms ± 0.6 ms
01 = 16 ms ± 4 ms
10 = 32 ms ± 4 ms
11 = 64 ms ± 4 ms
These bits are not cleared by any type of reset except RTCRST#.
Bit Description