Datasheet

LPC Interface Bridge Registers (D31:F0)
286 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register (PM—D31:F0)
Offset Address: A2–A3h Attribute: R/W, RO, R/WC
Default Value: 2000h Size: 16 bits
Lockable: No Usage: ACPI, Legacy
Power Well: RTC, SUS
Bit Description
15:13 Reserved
12 AG3_PP_EN - R/W. After G3 PHY Power Enable.
• When this bit is cleared (default), SLP_LAN# will be driven low upon exiting G3.
• When this bit is set, SLP_LAN# value is dependant on DSX_PP_DIS and Sx_PP_EN setting.
Refer to Section 3.12.9.4 for more details on SLP_LAN# value.
This bit is reset by RTCRST#.
11 Sx_PP_EN - R/W. Sx PHY Power Enable (Non G3 to Sx entry)
• When this bit is cleared (default), SLP_LAN# will be driven low in Sx/Moff.
• When this bit is set, SLP_LAN# will be driven high in Sx/Moff.
Refer to Section 3.12.9.4 for more details on SLP_LAN# value.
This bit is on VccSUS3_3 and is reset when Suspend is reset.
10:8 Reserved
7 DRAM Initialization Bit — R/W. This bit does not affect hardware functionality in any way. BIOS is
expected to set this bit prior to starting the DRAM initialization sequence and to clear this bit after
completing the DRAM initialization sequence. BIOS can detect that a DRAM initialization sequence
was interrupted by a reset by reading this bit during the boot sequence.
• If the bit is 1, then the DRAM initialization was interrupted.
• This bit is reset by the assertion of the RSMRST# pin.
6Reserved
5 Memory Placed in Self-Refresh (MEM_SR) — RO.
• If the bit is 1, DRAM should have remained powered and held in Self-Refresh through the last
power state transition (that is, the last time the system left S0).
• This bit is reset by the assertion of the RSMRST# pin.
4 System Reset Status (SRS) — R/WC. Software clears this bit by writing a 1 to it.
0 = SYS_RESET# button Not pressed.
1 = Intel® Xeon® Processor D-1500 Product Family sets this bit when the SYS_RESET# button is
pressed. BIOS is expected to read this bit and clear it, if it is set.
Notes:
1. This bit is also reset by RSMRST# and CF9h resets.
2. The SYS_RESET# is implemented in the Main power well. This pin must be properly isolated
and masked to prevent incorrectly setting this Suspend well status bit.
3 Processor Thermal Trip Status (CTS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the system is in an
S0 or S1 state.
Notes:
1. This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the shutdown and reboot
associated with the processor THRMTRIP# event.
2. The CF9h reset in the description refers to CF9h type core well reset which includes
SYS_RESET#, PCH_PWROK/SYS_PWROK low, SMBus hard reset, TCO Timeout. This type
of reset will clear CTS bit.