Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 285
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register (PM—D31:F0)
Offset Address: A0–A1h Attribute: R/W, RO, R/WLO
Default Value: 0000h Size: 16 bits
Lockable: No Usage: ACPI, Legacy
Power Well: Core
ACh–AFh PMIR Power Management Initialization 00000000h R/W, R/WLO
B8h–BBh GPI_ROUT GPI Routing Control Register 00000000h R/W
BCh–BFh GPI_ROUT2 GPI Routing Control Register #2 00000000h R/W
Table 7-9. Power Management PCI Register Address Map (PM—D31:F0) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Attribute
Bit Description
15 Reserved
14 GEN_PMCON_1 Field 4 — R/W. BIOS may write to this field.
13 GEN_PMCON_1 Field 3 — R/W. BIOS may write to this field.
12 GEN_PMCON_1 Field 2 — R/W. BIOS may write to this field.
11 GEN_PMCON_1 Field 1 — R/W. BIOS must program this field to 1b.
10 BIOS_PCI_EXP_EN — R/W. This bit acts as a global enable for the SCI associated with the
PCI Express* ports.
0 = The various PCI Express ports and processor cannot cause the PCI_EXP_STS bit to go
active.
1 = The various PCI Express ports and processor can cause the PCI_EXP_STS bit to go active.
9 PWRBTN_LVL — RO. This bit indicates the current state of the PWRBTN# signal.
0 = Low
1 = High
8:7 Reserved
6 SMI_LOCK_GP22 — R/WLO. When this bit is set, writes to GPI_ROUT2[7:6],
ALT_GPI_SMI_EN2[3], and GP_IO_SEL[22] will have no effect. Once the SMI_LOCK_GP22 bit is
set, writes of 0 to SMI_LOCK_GP22 have no effect (that is, once set, this bit can only be cleared
by PLTRST#).
5 SMI_LOCK_GP6 — R/WLO. When this bit is set, writes to GPI_ROUT[13:12],
ALT_GPI_SMI_EN[6] and GP_IO_SEL[6] will have no effect. Once the SMI_LOCK_GP6 bit is set,
writes of 0 to SMI_LOCK_GP6 have no effect (that is, once set, this bit can only be cleared by
PLTRST#).
4 SMI_LOCK — R/WLO. When this bit is set, writes to the GLB_SMI_EN bit (PMBASE + 30h, bit
0) will have no effect. Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will have no
effect (that is, once set, this bit can only be cleared by PLTRST#).
3 Pseudo CLKRUN_EN(PSEUDO_CLKRUN_EN) — R/W.
0 = Disable.
1 = Enable internal CLKRUN# logic to allow BDX PLL shutdown. This bit has no impact on state
of external CLKRUN# pin.
Notes:
1. PSEUDO_CLKRUN_EN bit does not result in STP_PCI# assertion to actually stop the
external PCICLK.
2. This bit should be set mutually exclusive with the CLKRUN_EN bit.
2 Reserved
1:0 Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control the rate at
which periodic SMI# is generated.
00 = 64 seconds
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds