Datasheet

LPC Interface Bridge Registers (D31:F0)
284 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8 Power Management Registers
The power management registers are distributed within the PCI Device 31: Function 0
space, as well as a separate I/O range. Each register is described below. Unless
otherwise indicated, bits are in the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to
a reserved bit, the value should always be 0. Software should not attempt to use the
value read from a reserved bit, as it may not be consistently 1 or 0.
7.8.1 Power Management PCI Configuration Registers (PM—
D31:F0)
Tab l e 7- 9 shows a small part of the configuration space for PCI Device 31: Function 0.
It includes only those registers dedicated for power management. Some of the
registers are only used for Legacy Power management schemes.
3 Full Reset (FULL_RST) — R/W. This bit is used to determine the states of SLP_S3#, SLP_S4#, and
SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1), after PCH_PWROK going
low (with RSMRST# high), or after two TCO timeouts.
0 = Intel® Xeon® Processor D-1500 Product Family will keep SLP_S3#, SLP_S4# and SLP_S5#
high.
1 = Intel® Xeon® Processor D-1500 Product Family will drive SLP_S3#, SLP_S4# and SLP_S5#
low for 3–5 seconds.
Note: When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion) in response
to SYS_RESET#, PWROK#, and Watchdog timer reset sources.
2 Reset Processor (RST_CPU) — R/W. When this bit transitions from a 0 to a 1, it initiates a hard or
soft reset, as determined by the SYS_RST bit (bit 1 of this register).
1 System Reset (SYS_RST) — R/W. This bit is used to determine a hard or soft reset to the
processor.
0 = When RST_CPU bit goes from 0 to 1, Intel® Xeon® Processor D-1500 Product Family performs
a soft reset by activating INIT# for 16 PCI clocks.
1 = When RST_CPU bit goes from 0 to 1, Intel® Xeon® Processor D-1500 Product Family performs
a hard reset by activating PLTRST# and SUS_STAT# active for a minimum of about 1
milliseconds. In this case, SLP_S3#, SLP_S4# and SLP_S5# state (assertion or de-assertion)
depends on FULL_RST bit setting. Intel® Xeon® Processor D-1500 Product Family main power
well is reset when this bit is 1. It also resets the resume well bits (except for those noted
throughout this document).
0Reserved
Bit Description
Table 7-9. Power Management PCI Register Address Map (PM—D31:F0) (Sheet 1 of 2)
Offset Mnemonic Register Name Default Attribute
A0h–A1h GEN_PMCON_1 General Power Management
Configuration 1
0000h R/W, R/WLO,
RO
A2–A3h GEN_PMCON_2 General Power Management
Configuration 2
2000h R/W, R/WC,
RO
A4h–A5h GEN_PMCON_3 General Power Management
Configuration 3
4206h R/W, R/WC,
RO, R/WL
A6h GEN_PMCON_LOCK General Power Management
Configuration Lock
00h RO, R/WL
A9h CIR4 Chipset Initialization Register 4 03h R/W, RO
AAh BM_BREAK_EN_2 BM_BREAK_EN Register #2 00h R/W, RO
ABh BM_BREAK_EN BM_BREAK_EN Register 00h R/W, RO