Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 283
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)
Register
I/O Address: 70h Attribute: R/W (special)
Default Value: 80h Size: 8 bits
Lockable: No Power Well: Core
Note: The RTC Index field is write-only for normal operation. This field can only be read in Alt-
Access Mode. Note, however, that this register is aliased to Port 74h (documented in
Ta b l e 7- 6 ), and all bits are readable at that address.
7.7.3 PORT92—Init Register
I/O Address: 92h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Core
7.7.4 COPROC_ERR—Coprocessor Error Register
I/O Address: F0h Attribute: WO
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Core
7.7.5 RST_CNT—Reset Control Register
I/O Address: CF9h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Core
Bits Description
7 NMI Enable (NMI_EN) — R/W (special).
0 = Enable NMI sources.
1 = Disable All NMI sources.
6:0 Real Time Clock Index Address (RTC_INDX) — R/W (special). This data goes to the RTC to
select which register or CMOS RAM address is being accessed.
Bit Description
7:2 Reserved
1 Alternate A20 Gate (ALT_A20_GATE) — R/W. Functionality reserved. A20M# functionality is not
supported.
0 INIT_NOW — R/W. When this bit transitions from a 0 to a 1, Intel® Xeon® Processor D-1500
Product Family will force INIT# active for 16 PCI clocks.
Bits Description
7:0 Coprocessor Error (COPROC_ERR) — WO. Any value written to this register will cause IGNNE# to
go active, if FERR# had generated an internal IRQ13. For FERR# to generate an internal IRQ13, the
COPROC_ERR_EN bit must be 1.
Bit Description
7:4 Reserved