Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 281
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.6.2.3 RTC_REGC—Register C (Flag Register)
RTC Index: 0Ch Attribute: RO
Default Value: 00U00000 (U: Undefined) Size: 8 bits
Lockable: No Power Well: RTC
Writes to Register C have no effect.
7.6.2.4 RTC_REGD—Register D (Flag Register)
RTC Index: 0Dh Attribute: R/W
Default Value: 10UUUUUU (U: Undefined) Size: 8 bits
Lockable: No Power Well: RTC
7.7 Processor Interface Registers
Ta b l e 7- 8 is the register address map for the processor interface registers.
2 Data Mode (DM) — R/W. This bit specifies either binary or BCD data representation. This bit is not
affected by RSMRST# nor any other reset signal.
0 = BCD
1 = Binary
1 Hour Format (HOURFORM) — R/W. This bit indicates the hour byte format. This bit is not affected
by RSMRST# nor any other reset signal.
0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and PM as one.
1 = Twenty-four hour mode.
0 Daylight Savings Legacy Software Support (DSLSWS) — R/W. Daylight savings functionality is
no longer supported. This bit is used to maintain legacy software support and has no associated
functionality. If BUC.DSO bit is set, the DSLSWS bit continues to be R/W.
Bit Description
Bit Description
7 Interrupt Request Flag (IRQF) — RO. IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE). This bit also
causes the RTC Interrupt to be asserted. This bit is cleared upon RSMRST# or a read of Register C.
6 Periodic Interrupt Flag (PF) — RO. This bit is cleared upon RSMRST# or a read of Register C.
0 = If no taps are specified using the RS bits in Register A, this flag will not be set.
1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is 1.
5 Alarm Flag (AF) — RO.
0 = This bit is cleared upon RTCRST# or a read of Register C.
1 = Alarm Flag will be set after all Alarm values match the current time.
4 Update-Ended Flag (UF) — RO.
0 = The bit is cleared upon RSMRST# or a read of Register C.
1 = Set immediately following an update cycle for each second.
3:0 Reserved. Will always report 0.
Bit Description
7 Valid RAM and Time Bit (VRT) — R/W.
0 = This bit should always be written as a 0 for write cycle, however it will return a 1 for read cycles.
1 = This bit is hardwired to 1 in the RTC power well.
6 Reserved. This bit always returns a 0 and should be cleared to 0 for write cycles.
5:0 Date Alarm — R/W. These bits store the date of month alarm value. If set to 000000b, then a don’t
care state is assumed. The host must configure the date alarm for these bits to do anything, yet they
can be written at any time. If the date alarm is not enabled, these bits will return 0s to mimic the
functionality of the Motorola 146818B. These bits are not affected by any reset assertion.