Datasheet

LPC Interface Bridge Registers (D31:F0)
280 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.6.2.2 RTC_REGB—Register B (General Configuration)
RTC Index: 0Bh Attribute: R/W
Default Value: U0U00UUU (U: Undefined) Size: 8 bits
Lockable: No Power Well: RTC
6:4 Division Chain Select (DV[2:0]) — R/W. These three bits control the divider chain for the
oscillator, and are not affected by RSMRST# or any other reset signal.
010 = Normal Operation
11X = Divider Reset
101 = Bypass 15 stages (test mode only)
100 = Bypass 10 stages (test mode only)
011 = Bypass 5 stages (test mode only)
001 = Invalid
000 = Invalid
3:0 Rate Select (RS[3:0]) — R/W. Selects one of 13 taps of the 15 stage divider chain. The selected
tap can generate a periodic interrupt if the PIE bit is set in Register B. Otherwise this tap will set the
PF flag of Register C. If the periodic interrupt is not to be used, these bits should all be cleared to 0.
RS3 corresponds to bit 3.
0000 = Interrupt never toggles
0001 = 3.90625 ms
0010 = 7.8125 ms
0011 = 122.070 µs
0100 = 244.141 µs
0101 = 488.281 µs
0110 = 976.5625 µs
0111 = 1.953125 ms
1000 = 3.90625 ms
1001 = 7.8125 ms
1010 = 15.625 ms
1011 = 31.25 ms
1100 = 62.5 ms
1101 = 125 ms
1110 = 250 ms
1111= 500 ms
Bit Description
Bit Description
7 Update Cycle Inhibit (SET) — R/W. Enables/Inhibits the update cycles. This bit is not affected by
RSMRST# nor any other reset signal.
0 = Update cycle occurs normally once each second.
1 = A current update cycle will abort and subsequent update cycles will not occur until SET is
returned to 0. When set is one, the BIOS may initialize time and calendar bytes safely.
Note: This bit should be set then cleared early in BIOS POST after each powerup directly after
coin-cell battery insertion.
6 Periodic Interrupt Enable (PIE) — R/W. This bit is cleared by RSMRST#, but not on any other
reset.
0 = Disable.
1 = Enable. Allows an interrupt to occur with a time base set with the RS bits of register A.
5 Alarm Interrupt Enable (AIE) — R/W. This bit is cleared by RTCRST#, but not on any other reset.
0 = Disable.
1 = Enable. Allows an interrupt to occur when the AF is set by an alarm match from the update
cycle. An alarm can occur once a second, one an hour, once a day, or one a month.
4 Update-Ended Interrupt Enable (UIE) — R/W. This bit is cleared by RSMRST#, but not on any
other reset.
0 = Disable.
1 = Enable. Allows an interrupt to occur when the update cycle ends.
3 Square Wave Enable (SQWE) — R/W. This bit serves no function in Intel® Xeon® Processor D-
1500 Product Family. It is left in this register bank to provide compatibility with the Motorola
146818B. Intel® Xeon® Processor D-1500 Product Family has no SQW pin. This bit is cleared by
RSMRST#, but not on any other reset.