Datasheet

Introduction
28 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
SPI_CS1# are used to access two separate SPI Flash components in Descriptor Mode.
SPI_CS2# is dedicated only to support Trusted Platform Module (TPM) on SPI (TPM can
be configured through Intel® Xeon® Processor D-1500 Product Family soft straps to
operate over LPC or SPI, but no more than 1 TPM is allowed in the system). SPI_CS2#
may not be used for any purpose other than TPM.
The SPI Flash Controller supports running instructions at 20 MHz, 33 MHz, and 50 MHz,
and can be used by Intel® Xeon® Processor D-1500 Product Family for BIOS code, to
provide chipset configuration settings, internal micro-processor code, and integrated
Gigabit Ethernet MAC/PHY configuration. The SPI Flash Controller supports the Serial
Flash Discoverable Parameter (SFDP) JEDEC standard that provides a consistent way of
describing the functional and feature capabilities of serial flash devices in a standard
set of internal parameter tables. The SPI Flash Controller queries these parameter
tables to discover the attributes to enable divergent features from multiple SPI part
vendors, such as Quad IO Fast Read capabilities or device storage capacity,
among others.
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
The DMA controller incorporates the logic of two 8237 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-
byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any
two of the seven DMA channels can be programmed to support fast Type-F transfers.
Channel 4 is reserved as a generic bus master request.
Intel® Xeon® Processor D-1500 Product Family supports LPC DMA, which is similar to
ISA DMA, through Intel® Xeon® Processor D-1500 Product Family DMA controller. LPC
DMA is handled through the use of the LDRQ# lines from peripherals and special
encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are
supported on the LPC interface.
The timer/counter block contains three counters that are equivalent in function to those
found in one 8254 programmable interval timer. These three counters are combined to
provide the system timer function, and speaker tone. The 14.318 MHz oscillator input
provides the clock source for these three counters.
Intel® Xeon® Processor D-1500 Product Family provides an ISA-compatible
Programmable Interrupt Controller (PIC) that incorporates the functionality of two 8259
interrupt controllers. The two interrupt controllers are cascaded so that 14 external and
two internal interrupts are possible. In addition, Intel® Xeon® Processor D-1500
Product Family supports a serial interrupt scheme.
All of the registers in these modules can be read and restored. This is required to save
and restore system state after power has been removed and restored to the platform.
Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA-compatible Programmable Interrupt controller (PIC)
described in the previous section, Intel® Xeon® Processor D-1500 Product Family
incorporates the Advanced Programmable Interrupt Controller (APIC).