Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 277
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
32 bit quantities)
The Redirection Table has a dedicated entry for each interrupt input pin. The
information in the Redirection Table is used to translate the interrupt manifestation on
the corresponding interrupt pin into an APIC message.
The APIC will respond to an edge triggered interrupt as long as the interrupt is held
until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery
status bit internally to the I/O APIC is set. The state machine will step ahead and wait
for an acknowledgment from the APIC unit that the interrupt message was sent. Only
then will the I/O APIC be able to recognize a new edge on that interrupt pin. That new
edge will only result in a new invocation of the handler if its acceptance by the
destination APIC causes the Interrupt Request Register bit to go from 0 to 1. (In other
words, if the interrupt was not already pending at the destination.)
Note: Delivery Mode encoding:
000 = Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination.
Trigger Mode can be edge or level.
Bit Description
63:56 Destination — R/W. If bit 11 of this entry is 0 (Physical), then bits 59:56 specifies an APIC ID. In
this case, bits 63:59 should be programmed by software to 0.
If bit 11 of this entry is 1 (Logical), then bits 63:56 specify the logical destination address of a set of
processors.
55:48 Extended Destination ID (EDID) — RO. These bits are sent to a local APIC only when in Processor
System Bus mode. They become bits 11:4 of the address.
47:17 Reserved
16 Mask — R/W.
0 = Not masked: An edge or level on this interrupt pin results in the delivery of the interrupt to the
destination.
1 = Masked: Interrupts are not delivered nor held pending. Setting this bit after the interrupt is
accepted by a local APIC has no effect on that interrupt. This behavior is identical to the device
withdrawing the interrupt before it is posted to the processor. It is software's responsibility to
deal with the case where the mask bit is set after the interrupt message has been accepted by
a local APIC unit but before the interrupt is dispensed to the processor.
15 Trigger Mode — R/W. This field indicates the type of signal on the interrupt pin that triggers an
interrupt.
0 = Edge triggered.
1 = Level triggered.
14 Remote IRR — R/W. This bit is used for level triggered interrupts; its meaning is undefined for edge
triggered interrupts.
0 = Reset when an EOI message is received from a local APIC.
1 = Set when Local APIC/s accept the level interrupt sent by the I/O APIC.
13 Interrupt Input Pin Polarity — R/W. This bit specifies the polarity of each interrupt signal
connected to the interrupt pins.
0 = Active high.
1 = Active low.
12 Delivery Status — RO. This field contains the current status of the delivery of this interrupt. Writes
to this bit have no effect.
0 = Idle. No activity for this interrupt.
1 = Pending. Interrupt has been injected, but delivery is not complete.
11 Destination Mode — R/W. This field determines the interpretation of the Destination field.
0 = Physical. Destination APIC ID is identified by bits 59:56.
1 = Logical. Destinations are identified by matching bit 63:56 with the Logical Destination in the
Destination Format Register and Logical Destination Register in each Local APIC.
10:8 Delivery Mode — R/W. This field specifies how the APICs listed in the destination field should act
upon reception of this signal. Certain Delivery Modes will only operate as intended when used in
conjunction with a specific trigger mode. These encodings are listed in the note below:
7:0 Vector — R/W. This field contains the interrupt vector for this interrupt. Values range between 10h
and FEh.