Datasheet

LPC Interface Bridge Registers (D31:F0)
276 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.5.5 ID—Identification Register
Index Offset: 00h Attribute: R/W
Default Value: 00000000h Size: 32 bits
The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the
APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset.
7.5.6 VER—Version Register
Index Offset: 01h Attribute: RO, R/WO
Default Value: 00170020h Size: 32 bits
Each I/O APIC contains a hardwired Version Register that identifies different
implementation of APIC and their versions. The maximum redirection entry information
also is in this register, to let software know how many interrupt are supported by this
APIC.
7.5.7 REDIR_TBL—Redirection Table Register
Index Offset: 10h–11h (vector 0) Attribute: R/W, RO
through 3E–3Fh
(vector 23)
Default Value: Bit 16 = 1. Size: 64 bits each,
All other bits undefined (accessed as two
Bit Description
31:8 Reserved. To provide for future expansion, the processor should always write a value of 0 to Bits
31:8.
7:0 Redirection Entry Clear — WO. When a write is issued to this register, the I/O APIC will check this
field, and compare it with the vector field for each entry in the I/O Redirection Table. When a match
is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared.
Bit Description
31:28 Reserved
27:24 APIC ID — R/W. Software must program this value before using the APIC.
23:16 Reserved
15 Scratchpad Bit
14:0 Reserved
Bit Description
31:24 Reserved
23:16 Maximum Redirection Entries (MRE) — R/WO. This is the entry number (0 being the lowest
entry) of the highest entry in the redirection table. It is equal to the number of interrupt input pins
minus one and is in the range 0 through 239. In Intel® Xeon® Processor D-1500 Product Family this
field is hardwired to 17h to indicate 24 interrupts.
BIOS must write to this field after PLTRST# to lockdown the value. this allows BIOS to utilize some of
the entries for its own purpose and thus advertising fewer IOxAPIC Redirection Entries to the OS.
15 Pin Assertion Register Supported (PRQ) — RO. Indicate that the IOxAPIC does not implement
the Pin Assertion Register.
14:8 Reserved
7:0 Version (VS) — RO. This is a version number that identifies the implementation version.