Datasheet
LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 275
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.5.2 IND—Index Register
Memory Address FEC_ _0000h Attribute: R/W
Default Value: 00h Size: 8 bits
The Index Register will select which APIC indirect register to be manipulated by
software. The selector values for the indirect registers are listed in Ta bl e 7- 5 . Software
will program this register to select the desired APIC internal register.
.
7.5.3 DAT—Data Register
Memory Address FEC_ _0000h Attribute: R/W
Default Value: 00000000h Size: 32 bits
This is a 32-bit register specifying the data to be read or written to the register pointed
to by the Index register. This register can only be accessed in DWord quantities.
7.5.4 EOIR—EOI Register
Memory Address FEC_ _0000h Attribute: R/W
Default Value: N/A Size: 32 bits
The EOI register is present to provide a mechanism to maintain the level triggered
semantics for level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower 8 bits written
to this register, and compare it with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit (Index Offset 10h,
bit 14) for that I/O Redirection Entry will be cleared.
Note: If multiple I/O Redirection entries, for any reason, assign the same vector for more
than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0.
The interrupt, which was prematurely reset, will not be lost because if its input
remained active when the Remote_IRR bit was cleared, the interrupt will be reissued
and serviced at a later time. Only bits 7:0 are actually used. Bits 31:8 are ignored by
Intel® Xeon® Processor D-1500 Product Family.
Note: To provide for future expansion, the processor should always write a value of 0 to Bits
31:8.
... ... ... ... ...
3E–3F REDIR_TBL23 Redirection Table 23 64 bits R/W, RO
40–FF — Reserved — RO
Table 7-5. APIC Indirect Registers
Index Mnemonic Register Name Size Type
Bit Description
7:0 APIC Index — R/W. This is an 8-bit pointer into the I/O APIC register table.
Bit Description
7:0 APIC Data — R/W. This is a 32-bit register for the data to be read or written to the APIC indirect
register (Figure 7-5) pointed to by the Index register (Memory Address FEC0_0000h).