Datasheet

LPC Interface Bridge Registers (D31:F0)
272 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.4.8 OCW2—Operational Control Word 2 Register
Offset Address: Master Controller – 020h Attribute: WO
Slave Controller – 0A0h Size: 8 bits
Default Value: Bit[4:0]=undefined, Bit[7:5]=001
Following a part reset or ICW initialization, the controller enters the fully nested mode
of operation. Non-specific EOI without rotation is the default. Both rotation mode and
specific EOI mode are disabled following initialization.
7.4.9 OCW3—Operational Control Word 3 Register
Offset Address: Master Controller – 020h Attribute: WO
Slave Controller – 0A0h Size: 8 bits
Default Value: Bit[6,0]=0, Bit[7,4:2]=undefined,
Bit[5,1]=1
Bit Description
7:5 Rotate and EOI Codes (R, SL, EOI) — WO. These three bits control the Rotate and End of Interrupt
modes and combinations of the two.
000 = Rotate in Auto EOI Mode (Clear)
001 = Non-specific EOI command
010 = No Operation
011 = *Specific EOI Command
100 = Rotate in Auto EOI Mode (Set)
101 = Rotate on Non-Specific EOI Command
110 = *Set Priority Command
111 = *Rotate on Specific EOI Command
*L0 – L2 Are Used
4:3 OCW2 Select — WO. When selecting OCW2, bits 4:3 = 00
2:0 Interrupt Level Select (L2, L1, L0) — WO. L2, L1, and L0 determine the interrupt level acted upon
when the SL bit is active. A simple binary code, outlined below, selects the channel for the command
to act upon. When the SL bit is inactive, these bits do not have a defined function; programming L2,
L1 and L0 to 0 is sufficient in this case.
Code Interrupt Level Code Interrupt Level
000b IRQ0/8 000b IRQ4/12
001b IRQ1/9 001b IRQ5/13
010b IRQ2/10 010b IRQ6/14
011b IRQ3/11 011b IRQ7/15
Bit Description
7 Reserved. Must be 0.
6 Special Mask Mode (SMM) — WO.
1 = The Special Mask Mode can be used by an interrupt service routine to dynamically alter the
system priority structure while the routine is executing, through selective enabling/disabling of
the other channel's mask bits. Bit 5, the ESMM bit, must be set for this bit to have any meaning.
5 Enable Special Mask Mode (ESMM) — WO.
0 = Disable. The SMM bit becomes a “don't care”.
1 = Enable the SMM bit to set or reset the Special Mask Mode.
4:3 OCW3 Select — WO. When selecting OCW3, bits 4:3 = 01
2 Poll Mode Command — WO.
0 = Disable. Poll Command is not issued.
1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt acknowledge
cycle. An encoded byte is driven onto the data bus, representing the highest priority level
requesting service.