Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 271
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.4.5 ICW3—Slave Controller Initialization Command Word 3
Register
Offset Address: A1h Attribute: WO
Default Value: All bits undefined Size: 8 bits
7.4.6 ICW4—Initialization Command Word 4 Register
Offset Address: Master Controller – 021h Attribute: WO
Slave Controller – 0A1h Size: 8 bits
Default Value: 01h
7.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)
Register
Offset Address: Master Controller – 021h Attribute: R/W
Slave Controller – 0A1h Size: 8 bits
Default Value: 00h
Bit Description
7:3 0 = These bits must be programmed to 0.
2:0 Slave Identification Code — WO. These bits are compared against the slave identification code
broadcast by the master controller from the trailing edge of the first internal INTA# pulse to the
trailing edge of the second internal INTA# pulse. These bits must be programmed to 02h to match
the code broadcast by the master controller. When 02h is broadcast by the master controller during
the INTA# sequence, the slave controller assumes responsibility for broadcasting the interrupt
vector.
Bit Description
7:5 0 = These bits must be programmed to 0.
4 Special Fully Nested Mode (SFNM) — WO.
0 = Should normally be disabled by writing a 0 to this bit.
1 = Special fully nested mode is programmed.
3 Buffered Mode (BUF) — WO.
0 = Must be programmed to 0 for Intel® Xeon® Processor D-1500 Product Family. This is non-
buffered mode.
2 Master/Slave in Buffered Mode — WO. Not used.
0 = Should always be programmed to 0.
1 Automatic End of Interrupt (AEOI) — WO.
0 = This bit should normally be programmed to 0. This is the normal end of interrupt.
1 = Automatic End of Interrupt (AEOI) mode is programmed.
0 Microprocessor Mode — WO.
1 = Must be programmed to 1 to indicate that the controller is operating in an Intel
Architecture-based system.
Bit Description
7:0 Interrupt Request Mask — R/W. When a 1 is written to any bit in this register, the corresponding
IRQ line is masked. When a 0 is written to any bit in this register, the corresponding IRQ mask bit is
cleared, and interrupt requests will again be accepted by the controller. Masking IRQ2 on the master
controller will also mask the interrupt requests from the slave controller.