Datasheet

LPC Interface Bridge Registers (D31:F0)
270 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.4.3 ICW2—Initialization Command Word 2 Register
Offset Address: Master Controller – 21h Attribute: WO
Slave Controller – A1h Size: 8 bits /controller
Default Value: All bits undefined
ICW2 is used to initialize the interrupt controller with the five most significant bits of
the interrupt vector address. The value programmed for bits[7:3] is used by the
processor to define the base address in the interrupt vector table for the interrupt
routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h
for the master controller and 70h for the slave controller.
7.4.4 ICW3—Master Controller Initialization Command Word 3
Register
Offset Address: 21h Attribute: WO
Default Value: All bits undefined Size: 8 bits
Bit Description
7:3 Interrupt Vector Base Address — WO. Bits [7:3] define the base address in the interrupt vector
table for the interrupt routines associated with each interrupt request level input.
2:0 Interrupt Request Level — WO. When writing ICW2, these bits should all be 0. During an interrupt
acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be
serviced. This is combined with bits [7:3] to form the interrupt vector driven onto the data bus
during the second INTA# cycle. The code is a three bit binary code:
Code Master Interrupt Slave Interrupt
000b IRQ0 IRQ8
001b IRQ1 IRQ9
010b IRQ2 IRQ10
011b IRQ3 IRQ11
100b IRQ4 IRQ12
101b IRQ5 IRQ13
110b IRQ6 IRQ14
111b IRQ7 IRQ15
Bit Description
7:3 0 = These bits must be programmed to 0.
2 Cascaded Interrupt Controller IRQ Connection — WO. This bit indicates that the slave controller
is cascaded on IRQ2. When IRQ8#–IRQ15 is asserted, it goes through the slave controller’s priority
resolver. The slave controller’s INTR output onto IRQ2. IRQ2 then goes through the master
controller’s priority solver. If it wins, the INTR signal is asserted to the processor, and the returning
interrupt acknowledge returns the interrupt vector for the slave controller.
1 = This bit must always be programmed to a 1.
1:0 0 = These bits must be programmed to 0.