Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 269
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: Refer to note addressing active-low interrupt sources in 8259 Interrupt Controllers
section (Section 3.8).
7.4.2 ICW1—Initialization Command Word 1 Register
Offset Address: Master Controller – 20h Attribute: WO
Slave Controller – A0h Size: 8 bits /controller
Default Value: All bits undefined
A write to Initialization Command Word 1 starts the interrupt controller initialization
sequence, during which the following occurs:
1. The Interrupt Mask register is cleared.
2. IRQ7 input is assigned priority 7.
3. The slave mode address is set to 7.
4. Special mask mode is cleared and Status Read is set to IRR.
Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to
complete the initialization sequence.
A1h A5h, A9h,
ADh, B1h,
B5h, B9h, BDh
Slave PIC ICW2 Init. Cmd Word 2 Undefined WO
Slave PIC ICW3 Init. Cmd Word 3 Undefined WO
Slave PIC ICW4 Init. Cmd Word 4 01h WO
Slave PIC OCW1 Op Ctrl Word 1 00h R/W
4D0h – Master PIC Edge/Level Triggered 00h R/W
4D1h – Slave PIC Edge/Level Triggered 00h R/W
Table 7-3. PIC Registers
Port Aliases Register Name Default Value Type
Bit Description
7:5 ICW/OCW Select — WO. These bits are MCS-85 specific, and not needed.
000 = Should be programmed to “000”
4 ICW/OCW Select — WO.
1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4 sequence.
3 Edge/Level Bank Select (LTIM) — WO. Disabled. Replaced by the edge/level triggered control
registers (ELCR, D31:F0:4D0h, D31:F0:4D1h).
2ADI — WO.
0 = Ignored for Intel® Xeon® Processor D-1500 Product Family. Should be programmed to 0.
1 Single or Cascade (SNGL) — WO.
0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode.
0 ICW4 Write Required (IC4) — WO.
1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be programmed.