Datasheet
LPC Interface Bridge Registers (D31:F0)
268 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.3.3 Counter Access Ports Register
I/O Address: Counter 0 – 40h,
Counter 1 – 41h, Attribute: R/W
Counter 2 – 42h
Default Value: All bits undefined Size: 8 bits
7.4 8259 Interrupt Controller (PIC) Registers
7.4.1 Interrupt Controller I/O MAP
The interrupt controller registers are located at 20h and 21h for the master controller
(IRQ 0–7), and at A0h and A1h for the slave controller (IRQ 8–13). These registers
have multiple functions, depending upon the data written to them. Tabl e 7- 3 shows the
different register possibilities for each address.
3:1 Mode Selection Status — RO. These bits return the counter mode programming. The binary code
returned matches the code used to program the counter mode, as listed under the bit function
above.
000 = Mode 0 — Out signal on end of count (=0)
001 = Mode 1 — Hardware retriggerable one-shot
x10 = Mode 2 — Rate generator (divide by n counter)
x11 = Mode 3 — Square wave output
100 = Mode 4 — Software triggered strobe
101 = Mode 5 — Hardware triggered strobe
0 Countdown Type Status — RO. This bit reflects the current countdown type.
0 = Binary countdown
1 = Binary Coded Decimal (BCD) countdown.
Bit Description
Bit Description
7:0 Counter Port — R/W. Each counter port address is used to program the 16-bit Count Register. The
order of programming, either LSB only, MSB only, or LSB then MSB, is defined with the Interval
Counter Control Register at port 43h. The counter port is also used to read the current count from the
Count Register, and return the status of the counter programming following a Read Back Command.
Table 7-3. PIC Registers
Port Aliases Register Name Default Value Type
20h 24h, 28h,
2Ch, 30h,
34h, 38h, 3Ch
Master PIC ICW1 Init. Cmd Word 1 Undefined WO
Master PIC OCW2 Op Ctrl Word 2 001XXXXXb WO
Master PIC OCW3 Op Ctrl Word 3 X01XXX10b WO
21h 25h, 29h,
2Dh, 31h,
35h, 39h, 3Dh
Master PIC ICW2 Init. Cmd Word 2 Undefined WO
Master PIC ICW3 Init. Cmd Word 3 Undefined WO
Master PIC ICW4 Init. Cmd Word 4 01h WO
Master PIC OCW1 Op Ctrl Word 1 00h R/W
A0h A4h, A8h,
ACh, B0h,
B4h, B8h, BCh
Slave PIC ICW1 Init. Cmd Word 1 Undefined WO
Slave PIC OCW2 Op Ctrl Word 2 001XXXXXb WO
Slave PIC OCW3 Op Ctrl Word 3 X01XXX10b WO