Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 265
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.3 Timer I/O Registers
7.3.1 TCW—Timer Control Word Register
I/O Address: 43h Attribute: WO
Default Value: All bits undefined Size: 8 bits
This register is programmed prior to any counter being accessed to specify counter
modes. Following part reset, the control words for each register are undefined and each
counter output is 0. Each timer must be programmed to bring it into a known state.
3:0 Channel Mask Bits — R/W. This register permits all four channels to be simultaneously enabled/
disabled instead of enabling/disabling each channel individually, as is the case with the Mask
Register – Write Single Mask Bit. In addition, this register has a read path to allow the status of the
channel mask bits to be read. A channel's mask bit is automatically set to 1 when the Current Byte/
Word Count Register reaches terminal count (unless the channel is in auto-initialization mode).
Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0 enables the
corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master Clear. When read, bits
[3:0] indicate the DMA channel [3:0] ([7:4]) mask status.
Bit 0 = Channel 0 (4)1 = Masked, 0 = Not Masked
Bit 1 = Channel 1 (5)1 = Masked, 0 = Not Masked
Bit 2 = Channel 2 (6)1 = Masked, 0 = Not Masked
Bit 3 = Channel 3 (7)1 = Masked, 0 = Not Masked
Note: Disabling channel 4 also disables channels 0–3 due to the cascade of channels
0–3 through channel 4.
Port Aliases Register Name Default Value Type
40h 50h Counter 0 Interval Time Status Byte Format 0XXXXXXXb RO
Counter 0 Counter Access Port Undefined R/W
41h 51h Counter 1 Interval Time Status Byte Format 0XXXXXXXb RO
Counter 1 Counter Access Port Undefined R/W
42h 52h Counter 2 Interval Time Status Byte Format 0XXXXXXXb RO
Counter 2 Counter Access Port Undefined R/W
43h 53h Timer Control Word Undefined WO
Timer Control Word Register XXXXXXX0b WO
Counter Latch Command X0h WO
Bit Description
Bit Description
7:6 Counter Select — WO. The Counter Selection bits select the counter the control word acts upon as
shown below. The Read Back Command is selected when bits[7:6] are both 1.
00 = Counter 0 select
01 = Counter 1 select
10 = Counter 2 select
11 = Read Back Command
5:4 Read/Write Select — WO. These bits are the read/write control bits. The actual counter
programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for
counter 2).
00 = Counter Latch Command
01 = Read/Write Least Significant Byte (LSB)
10 = Read/Write Most Significant Byte (MSB)
11 = Read/Write LSB then MSB