Datasheet
LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 263
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.2.6 DMA_WRSMSK—DMA Write Single Mask Register
I/O Address: Ch. #0–3 = 0Ah;
Ch. #4–7 = D4h Attribute: WO
Default Value: 0000 01xx Size: 8 bits
Lockable: No Power Well: Core
7.2.7 DMACH_MODE—DMA Channel Mode Register
I/O Address: Ch. #0–3 = 0Bh;
Ch. #4–7 = D6h Attribute: WO
Default Value: 0000 00xx Size: 8 bits
Lockable: No Power Well: Core
Bit Description
7:3 Reserved. Must be 0.
2 Channel Mask Select — WO.
0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0]. Therefore,
only one channel can be masked / unmasked at a time.
1 = Disable DREQ for the selected channel.
1:0 DMA Channel Select — WO. These bits select the DMA Channel Mode Register to program.
00 = Channel 0 (4)
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
Bit Description
7:6 DMA Transfer Mode — WO. Each DMA channel can be programmed in one of four different modes:
00 = Demand mode
01 = Single mode
10 = Reserved
11 = Cascade mode
5 Address Increment/Decrement Select — WO. This bit controls address increment/decrement
during DMA transfers.
0 = Address increment. (default after part reset or Master Clear)
1 = Address decrement.
4 Autoinitialize Enable — WO.
0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count. A part reset
or Master Clear disables autoinitialization.
1 = DMA restores the Base Address and Count registers to the current registers following a terminal
count (TC).
3:2 DMA Transfer Type — WO. These bits represent the direction of the DMA transfer. When the
channel is programmed for cascade mode, (bits [7:6] = 11) the transfer type is irrelevant.
00 = Verify – No I/O or memory strobes generated
01 = Write – Data transferred from the I/O devices to memory
10 = Read – Data transferred from memory to the I/O device
11 = Invalid
1:0 DMA Channel Select — WO. These bits select the DMA Channel Mode Register that will be written
by bits [7:2].
00 = Channel 0 (4)
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)