Datasheet

LPC Interface Bridge Registers (D31:F0)
262 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.2.3 DMAMEM_LP—DMA Memory Low Page Registers
I/O Address: Ch. #0 = 87h; Ch. #1 = 83h
Ch. #2 = 81h; Ch. #3 = 82h
Ch. #5 = 8Bh; Ch. #6 = 89h
Ch. #7 = 8Ah; Attribute: R/W
Default Value: Undefined Size: 8 bits
Lockable: No Power Well: Core
7.2.4 DMACMD—DMA Command Register
I/O Address: Ch. #0–3 = 08h;
Ch. #4–7 = D0h Attribute: WO
Default Value: Undefined Size: 8 bits
Lockable: No Power Well: Core
7.2.5 DMASTA—DMA Status Register
I/O Address: Ch. #0–3 = 08h;
Ch. #4–7 = D0h Attribute: RO
Default Value: Undefined Size: 8 bits
Lockable: No Power Well: Core
Bit Description
7:0 DMA Low Page (ISA Address bits [23:16]) — R/W. This register works in conjunction with the DMA
controller's Current Address Register to define the complete 24-bit address for the DMA channel.
This register remains static throughout the DMA transfer. Bit 16 of this register is ignored when in
16 bit I/O count by words mode as it is replaced by the bit 15 shifted out from the current address
register.
Bit Description
7:5 Reserved. Must be 0.
4 DMA Group Arbitration Priority — WO. Each channel group is individually assigned either fixed or
rotating arbitration priority. At part reset, each group is initialized in fixed priority.
0 = Fixed priority to the channel group
1 = Rotating priority to the group.
3 Reserved. Must be 0.
2 DMA Channel Group Enable — WO. Both channel groups are enabled following part reset.
0 = Enable the DMA channel group.
1 = Disable. Disabling channel group 4–7 also disables channel group 0–3, which is cascaded
through channel 4.
1:0 Reserved. Must be 0.
Bit Description
7:4 Channel Request Status — RO. When a valid DMA request is pending for a channel, the
corresponding bit is set to 1. When a DMA request is not pending for a particular channel, the
corresponding bit is set to 0. The source of the DREQ may be hardware or a software request.
Channel 4 is the cascade channel; thus, the request status of channel 4 is a logical OR of the request
status for channels 0 through 3.
4 = Channel 0
5 = Channel 1 (5)
6 = Channel 2 (6)
7 = Channel 3 (7)
3:0 Channel Terminal Count Status — RO. When a channel reaches terminal count (TC), its status bit
is set to 1. If TC has not been reached, the status bit is cleared to 0. Channel 4 is programmed for
cascade; thus, the TC bit response for channel 4 is irrelevant:
0 = Channel 0
1 = Channel 1 (5)
2 = Channel 2 (6)
3 = Channel 3 (7)