Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 259
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.39.3 FVEC2—Feature Vector Register 2
FVECIDX.IDX: 0010b Attribute: RO
Default Value: See Description Size: 32 bits
Power Well: Core
7.1.39.4 FVEC3—Feature Vector Register 3
FVECIDX.IDX: 0011b Attribute: RO
Default Value: See Description Size: 32 bits
Power Well: Core
7.1.40 RCBA—Root Complex Base Address Register (LPC I/F—
D31:F0)
Offset Address: F0–F3h Attribute: R/W
Default Value: 00000000h Size: 32 bits
7.2 DMA I/O Registers
Bit Description
31:22 Reserved
21 PCI Express* Ports 7 and 8— RO
0 = Capable
1 = Disabled
20:18 Reserved
17 Intel® Xeon® Processor D-1500 Product Family Integrated Graphics Support Capability — RO
0 = Capable
1 = Disabled
16:0 Reserved
Bit Description
31:14 Reserved
13 Data Center Manageability Interface (DCMI) Capability — RO
0 = Capable
1 = Disabled
12 Node Manager Capability — RO
0 = Capable
1 = Disabled
11:0 Reserved
Bit Description
31:14 Base Address (BA) — R/W. Base Address for the root complex register block decode range. This
address is aligned on a 16-KB boundary.
13:1 Reserved
0 Enable (EN) — R/W. When set, this bit enables the range specified in BA to be claimed as the Root
Complex Register Block.
Table 7-2. DMA Registers (Sheet 1 of 2)
Port Alias Register Name Default Type
00h 10h Channel 0 DMA Base and Current Address Undefined R/W
01h 11h Channel 0 DMA Base and Current Count Undefined R/W
02h 12h Channel 1 DMA Base and Current Address Undefined R/W
03h 13h Channel 1 DMA Base and Current Count Undefined R/W