Datasheet

LPC Interface Bridge Registers (D31:F0)
258 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.38 FVECD—Feature Vector Data Register (LPC I/F—D31:F0)
Offset Address: E8h–EBh Attribute: RO
Default Value: See Description Size: 32 bits
Power Well: Core
7.1.39 Feature Vector Space
7.1.39.1 FVEC0—Feature Vector Register 0
FVECIDX.IDX: 0000b Attribute: RO
Default Value: See Description Size: 32 bits
Power Well: Core
7.1.39.2 FVEC1—Feature Vector Register 1
FVECIDX.IDX: 0001b Attribute: RO
Default Value: See Description Size: 32 bits
Power Well: Core
Bit Description
31:0 Data (DATA) — RO. 32-bit data value that is read from the Feature Vector offset pointed to by
FVECIDX.
Bit Description
31:12 Reserved
11:10 USB Port Count Capability — RO
00 = 14 ports
01 = 12 ports
10 = 10 ports
11 = Reserved
9:8 Reserved
7 RAID Capability Bit 1 — RO
See bit 5 Description.
6 SATA Ports 2 and 3 — RO
0 = Capable
1 = Disabled
5:4 Reserved
3 SATA Port 1 6 Gb/s Capability— RO
0 = Capable
1 = Disabled
2 SATA Port 0 6 Gb/s Capability— RO
0 = Capable
1 = Disabled
1 PCI Interface Capability — RO
0 = Capable
1 = Disabled
0 Reserved
Bit Description
31:23 Reserved
22 USB Redirect (USBr) Capability— RO
0 = Capable
1 = Disabled
21:0 Reserved