Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 257
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.34 FDCAP—Feature Detection Capability ID Register (LPC I/
F—D31:F0)
Offset Address: E0h–E1h Attribute: RO
Default Value: 0009h Size: 16 bits
Power Well: Core
7.1.35 FDLEN—Feature Detection Capability Length Register
(LPC I/F—D31:F0)
Offset Address: E2h Attribute: RO
Default Value: 0Ch Size: 8 bits
Power Well: Core
7.1.36 FDVER—Feature Detection Version Register (LPC I/F—
D31:F0)
Offset Address: E3h Attribute: RO
Default Value: 10h Size: 8 bits
Power Well: Core
7.1.37 FVECIDX—Feature Vector Index Register (LPC I/F—
D31:F0)
Offset Address: E4h–E7h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Power Well: Core
Bit Description
15:8 Next Item Pointer (NEXT) — RO. Configuration offset of the next Capability Item. 00h indicates
the last item in the Capability List.
7:0 Capability ID — RO. Indicates a Vendor Specific Capability
Bit Description
7:0 Capability Length — RO. Indicates the length of this Vendor Specific capability, as required by PCI
Specification.
Bit Description
7:4 Vendor-Specific Capability ID — RO. A value of 1h in this 4-bit field identifies this Capability as
Feature Detection Type. This field allows software to differentiate the Feature Detection Capability
from other Vendor-Specific capabilities
3:0 Capability Version — RO. This field indicates the version of the Feature Detection capability
Bit Description
31:6 Reserved
5:2 Index (IDX) — R/W. 4-bit index pointer into the 64-byte Feature Vector space. Data is read from
the FVECD register. This points to a DWord register.
1:0 Reserved