Datasheet

LPC Interface Bridge Registers (D31:F0)
252 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.28 ULKMC—USB Legacy Keyboard / Mouse Control Register
(LPC I/F—D31:F0)
Offset Address: 94h–97h Attribute: RO, R/WC, R/W
Default Value: 00002000h Size: 32 bits
Power Well: Core
15:2 Generic I/O Decode Range 4 Base Address (GEN4_BASE) — R/W.
Note: Intel® Xeon® Processor D-1500 Product Family Does not provide decode down to the word
or byte level
1 Reserved
0 Generic Decode Range 4 Enable (GEN4_EN) — R/W.
0 = Disable.
1 = Enable the GEN4 I/O range to be forwarded to the LPC I/F
Bit Description
Bit Description
31:16 Reserved
15 SMI Caused by End of Pass-Through (SMIBYENDPS) — R/WC. This bit indicates if the event
occurred. Even if the corresponding enable bit is not set in bit 7, this bit will still be active. It is up to
the SMM code to use the enable bit to determine the exact cause of the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred
14:12 Reserved
11 SMI Caused by Port 64 Write (TRAPBY64W) — R/WC. This bit indicates if the event occurred.
Even if the corresponding enable bit is not set in bit 3, this bit will still be active. It is up to the SMM
code to use the enable bit to determine the exact cause of the SMI#. The A20Gate Pass-Through
Logic allows specific port 64h writes to complete without setting this bit.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
10 SMI Caused by Port 64 Read (TRAPBY64R) — R/WC. This bit indicates if the event occurred.
Even if the corresponding enable bit is not set in bit 2, this bit will still be active. It is up to the SMM
code to use the enable bit to determine the exact cause of the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
9 SMI Caused by Port 60 Write (TRAPBY60W) — R/WC. This bit indicates if the event occurred.
Even if the corresponding enable bit is not set in bit 1, this bit will still be active. It is up to the SMM
code to use the enable bit to determine the exact cause of the SMI#. The A20Gate Pass-Through
Logic allows specific port 64h writes to complete without setting this bit.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
8 SMI Caused by Port 60 Read (TRAPBY60R) — R/WC. This bit indicates if the event occurred.
Even if the corresponding enable bit is not set in the bit 0, this bit will still be active. It is up to the
SMM code to use the enable bit to determine the exact cause of the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
7 SMI at End of Pass-Through Enable (SMIATENDPS) — R/W. This bit enables SMI at the end of
a pass-through. This can occur if an SMI is generated in the middle of a pass-through, and needs to
be serviced later.
0 = Disable
1 = Enable
6 Pass Through State (PSTATE) — RO.
0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to 0.
1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence.
5 A20Gate Pass-Through Enable (A20PASSEN) — R/W.
0 = Disable.
1 = Enable. Allows A20GATE sequence Pass-Through function. A specific cycle sequence involving
writes to port 60h and 64h does not result in the setting of the SMI status bits.
Note: A20M# functionality is not supported.