Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 251
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.25 GEN2_DEC—LPC I/F Generic Decode Range 2 Register
(LPC I/F—D31:F0)
Offset Address: 88h–8Bh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Power Well: Core
7.1.26 GEN3_DEC—LPC I/F Generic Decode Range 3 Register
(LPC I/F—D31:F0)
Offset Address: 8Ch–8Eh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Power Well: Core
7.1.27 GEN4_DEC—LPC I/F Generic Decode Range 4 Register
(LPC I/F—D31:F0)
Offset Address: 90h–93h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Power Well: Core
Bit Description
31:24 Reserved
23:18 Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position indicates that any
value in the corresponding address bit in a received cycle will be treated as a match. The
corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6
bits of the DWord address, allowing for decoding blocks up to 256 bytes in size.
17:16 Reserved
15:2 Generic I/O Decode Range 2 Base Address (GEN1_BASE) — R/W.
Note: Intel® Xeon® Processor D-1500 Product Family does not provide decode down to the word
or byte level.
1 Reserved
0 Generic Decode Range 2 Enable (GEN2_EN) — R/W.
0 = Disable.
1 = Enable the GEN2 I/O range to be forwarded to the LPC I/F
Bit Description
31:24 Reserved
23:18 Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position indicates that any
value in the corresponding address bit in a received cycle will be treated as a match. The
corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6
bits of the DWord address, allowing for decoding blocks up to 256 bytes in size.
17:16 Reserved
15:2 Generic I/O Decode Range 3 Base Address (GEN3_BASE) — R/W.
Note: Intel® Xeon® Processor D-1500 Product Family Does not provide decode down to the word
or byte level
1 Reserved
0 Generic Decode Range 3 Enable (GEN3_EN) — R/W.
0 = Disable.
1 = Enable the GEN3 I/O range to be forwarded to the LPC I/F
Bit Description
31:24 Reserved
23:18 Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position indicates that any
value in the corresponding address bit in a received cycle will be treated as a match. The
corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6
bits of the DWord address, allowing for decoding blocks up to 256 bytes in size.
17:16 Reserved