Datasheet

LPC Interface Bridge Registers (D31:F0)
250 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.24 GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0)
Offset Address: 84h–87h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Power Well: Core
10 KBC_LPC_EN — R/W. Keyboard Enable.
0 = Disable.
1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This range is used
for a microcontroller.
9 GAMEH_LPC_EN — R/W. High Gameport Enable
0 = Disable.
1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This range is used
for a gameport.
8 GAMEL_LPC_EN — R/W. Low Gameport Enable
0 = Disable.
1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This range is used
for a gameport.
7:4 Reserved
3 FDD_LPC_EN — R/W. Floppy Drive Enable
0 = Disable.
1 = Enables the decoding of the FDD range to the LPC interface. This range is selected in the
LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 12).
2 LPT_LPC_EN — R/W. Parallel Port Enable
0 = Disable.
1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in the
LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 9:8).
1 COMB_LPC_EN — R/W. Com Port B Enable
0 = Disable.
1 = Enables the decoding of the COMB range to the LPC interface. This range is selected in the
LPC_COM Decode Range Register (D31:F0:80h, bits 6:4).
0 COMA_LPC_EN — R/W. Com Port A Enable
0 = Disable.
1 = Enables the decoding of the COMA range to the LPC interface. This range is selected in the
LPC_COM Decode Range Register (D31:F0:80h, bits 3:2).
Bit Description
Bit Description
31:24 Reserved
23:18 Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position indicates that any
value in the corresponding address bit in a received cycle will be treated as a match. The
corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6
bits of the DWord address, allowing for decoding blocks up to 256 bytes in size.
17:16 Reserved
15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W.
Note: Intel® Xeon® Processor D-1500 Product Family does not provide decode down to the word
or byte level
1 Reserved
0 Generic Decode Range 1 Enable (GEN1_EN) — R/W.
0 = Disable.
1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F