Datasheet

Introduction
Intel® Xeon® Processor D-1500 Product Family 25
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
1.1.1 Chapter Descriptions
Chapter 1, “Introduction” introduces Intel® Xeon® Processor D-1500 Product Family,
provides information on the organization of the manual and gives a general overview of
Intel® Xeon® Processor D-1500 Product Family.
Chapter 2, “Intel® Xeon® Processor D-1500 Product Family and System
Clocks” provides a list of each clock domain associated with Intel® Xeon® Processor
D-1500 Product Family.
Chapter 3, “Functional Description” provides a detailed description of the functions in
Intel® Xeon® Processor D-1500 Product Family.
Chapter 4, “Register and Memory Mapping” provides an overview of the registers, fixed
I/O ranges, variable I/O ranges and memory ranges decoded by Intel® Xeon®
Processor D-1500 Product Family.
Chapter 5, “Chipset Configuration Registers” provides a detailed description of registers
and base functionality that is related to chipset configuration. It contains the root
complex register block, which describes the behavior of the upstream internal link.
Chapter 6, “Gigabit LAN Configuration Registers” provides a detailed description
of registers that reside in Intel® Xeon® Processor D-1500 Product Family’s integrated
LAN controller. The integrated LAN Controller resides at Device 25, Function 0
(D25:F0).
Chapter 7, “LPC Interface Bridge Registers (D31:F0)” provides a detailed
description of registers that reside in the LPC bridge. This bridge resides at Device 31,
Function 0 (D31:F0). This function contains registers for many different units within
Intel® Xeon® Processor D-1500 Product Family including DMA, Timers, Interrupts,
Processor Interface, GPIO, Power Management, System Management and RTC.
Chapter 8, “SATA Controller Registers (D31:F2)” provides a detailed description of
registers that reside in the SATA controller #1. This controller resides at Device 31,
Function 2 (D31:F2).
Chapter 9, “PCI Configuration Registers (SATA–D31:F5)”
provides a detailed description of registers that
reside in the SATA controller #2. This controller resides at Device 31, Function 5
(D31:F5).
Chapter 10, “EHCI Controller Registers (D29:F0)” provides a detailed description of
registers that reside in the two EHCI host controllers. These controllers reside at Device
29, Function 0 (D29:F0) and Device 26, Function 0 (D26:F0).
Chapter 11, “xHCI Controller Registers (D20:F0)” provides a detailed description of
registers that reside in the xHCI. This controller resides at Device 20, Function 0
(D20:F0).
Intel
®
Virtualization Technology http://www.intel.com/technology/virtualization/index.htm
SFF-8485 Specification for Serial GPIO (SGPIO) Bus,
Revision 0.7
http://www.intel.com/technology/virtualization/index.htm
Advanced Host Controller Interface specification for Serial
ATA, Revision 1.3
http://www.intel.com/technology/serialata/ahci.htm
Table 1-1. Industry Specifications (Sheet 2 of 2)
Specification Location