Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 249
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.22 LPC_I/O_DEC—I/O Decode Ranges Register (LPC I/F—
D31:F0)
Offset Address: 80h Attribute: R/W
Default Value: 0000h Size: 16 bits
7.1.23 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)
Offset Address: 82h–83h Attribute: R/W
Default Value: 0000h Size: 16 bits
Power Well: Core
Bit Description
15:13 Reserved
12 FDD Decode Range — R/W. Determines which range to decode for the FDD Port
0 = 3F0h–3F5h, 3F7h (Primary)
1 = 370h–375h, 377h (Secondary)
11:10 Reserved
9:8 LPT Decode Range — R/W. This field determines which range to decode for the LPT Port.
00 = 378h–37Fh and 778h–77Fh
01 = 278h–27Fh (port 279h is read only) and 678h–67Fh
10 = 3BCh –3BEh and 7BCh–7BEh
11 = Reserved
7 Reserved
6:4 COMB Decode Range — R/W. This field determines which range to decode for the COMB Port.
000 = 3F8h–3FFh (COM1)
001 = 2F8h–2FFh (COM2)
010 = 220h–227h
011 = 228h–22Fh
100 = 238h–23Fh
101 = 2E8h–2EFh (COM4)
110 = 338h–33Fh
111 = 3E8h–3EFh (COM3)
3 Reserved
2:0 COMA Decode Range — R/W. This field determines which range to decode for the COMA Port.
000 = 3F8h–3FFh (COM1)
001 = 2F8h–2FFh (COM2)
010 = 220h–227h
011 = 228h–22Fh
100 = 238h–23Fh
101 = 2E8h–2EFh (COM4)
110 = 338h–33Fh
111 = 3E8h–3EFh (COM3)
Bit Description
15:14 Reserved
13 CNF2_LPC_EN — R/W. Microcontroller Enable #2.
0 = Disable.
1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This range is used
for a microcontroller.
12 CNF1_LPC_EN — R/W. Super I/O Enable.
0 = Disable.
1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This range is used
for Super I/O devices.
11 MC_LPC_EN — R/W. Microcontroller Enable # 1.
0 = Disable.
1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This range is used
for a microcontroller.