Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 247
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.18 SIRQ_CNTL—Serial IRQ Control Register (LPC I/F—
D31:F0)
Offset Address: 64h Attribute: R/W, RO
Default Value: 10h Size: 8 bits
Lockable: No Power Well: Core
7.1.19 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register
(LPC I/F—D31:F0)
Offset Address: PIRQE – 68h, PIRQF – 69h, Attribute: R/W
PIRQG – 6Ah, PIRQH – 6Bh
Default Value: 80h Size: 8 bits
Lockable: No Power Well: Core
Bit Description
7 Serial IRQ Enable (SIRQEN) — R/W.
0 = The buffer is input only and internally SERIRQ will be a 1.
1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ.
6 Serial IRQ Mode Select (SIRQMD) — R/W.
0 = The serial IRQ machine will be in quiet mode.
1 = The serial IRQ machine will be in continuous mode.
Note: For systems using Quiet Mode, this bit should be set to 1 (Continuous Mode) for at least one
frame after coming out of reset before switching back to Quiet Mode. Failure to do so will
result in Intel® Xeon® Processor D-1500 Product Family not recognizing SERIRQ interrupts.
5:2 Serial IRQ Frame Size (SIRQSZ) — RO. Fixed field that indicates the size of the SERIRQ frame as
21 frames.
1:0 Start Frame Pulse Width (SFPW) — R/W. This is the number of PCI clocks that the SERIRQ pin will
be driven low by the serial IRQ machine to signal a start frame. In continuous mode, Intel® Xeon®
Processor D-1500 Product Family will drive the start frame for the number of clocks specified. In
quiet mode, Intel® Xeon® Processor D-1500 Product Family will drive the start frame for the number
of clocks specified minus one, as the first clock was driven by the peripheral.
00 = 4 clocks
01 = 6 clocks
10 = 8 clocks
11 = Reserved
Bit Description
7 Interrupt Routing Enable (IRQEN) — R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
Note: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The
value of this bit may subsequently be changed by the OS when setting up for I/O APIC
interrupt delivery mode.
6:4 Reserved
3:0 IRQ Routing — R/W. (ISA compatible.)
Value IRQ Value IRQ
0000b Reserved 1000b Reserved
0001b Reserved 1001b IRQ9
0010b Reserved 1010b IRQ10
0011b IRQ3 1011b IRQ11
0100b IRQ4 1100b IRQ12
0101b IRQ5 1101b Reserved
0110b IRQ6 1110b IRQ14
0111b IRQ7 1111b IRQ15