Datasheet

LPC Interface Bridge Registers (D31:F0)
246 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register
(LPC I/F—D31:F0)
Offset Address: PIRQA – 60h, PIRQB – 61h, Attribute: R/W
PIRQC – 62h, PIRQD – 63h
Default Value: 80h Size: 8 bits
Lockable: No Power Well: Core
0 GPIO Lockdown Enable (GLE) — R/W. This bit enables lockdown of the following GPIO registers:
• Offset 00h: GPIO_USE_SEL
• Offset 04h: GP_IO_SEL
• Offset 0Ch: GP_LVL
• Offset 30h: GPIO_USE_SEL2
• Offset 34h: GP_IO_SEL2
• Offset 38h: GP_LVL2
• Offset 40h: GPIO_USE_SEL3
• Offset 44h: GP_IO_SEL3
• Offset 48h: GP_LVL3
• Offset 60h: GP_RST_SEL
0 = Disable.
1 = Enable.
When this bit is written from 1-to-0, an SMI# is generated, if enabled. This ensures that only SMM
code can change the above GPIO registers after they are locked down.
Bit Description
Bit Description
7 Interrupt Routing Enable (IRQEN) — R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in
bits[3:0].
1 = The PIRQ is not routed to the 8259.
Note: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used.
The value of this bit may subsequently be changed by the OS when setting up for I/O
APIC interrupt delivery mode.
6:4 Reserved
3:0 IRQ Routing — R/W. (ISA compatible.)
Value IRQ Value IRQ
0000b Reserved 1000b Reserved
0001b Reserved 1001b IRQ9
0010b Reserved 1010b IRQ10
0011b IRQ3 1011b IRQ11
0100b IRQ4 1100b IRQ12
0101b IRQ5 1101b Reserved
0110b IRQ6 1110b IRQ14
0111b IRQ7 1111b IRQ15