Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 245
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.15 GPIOBASE—GPIO Base Address Register (LPC I/F —
D31:F0)
Offset Address: 48h–4Bh Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
7.1.16 GC—GPIO Control Register (LPC I/F — D31:F0)
Offset Address: 4Ch Attribute: R/W
Default Value: 00h Size: 8 bits
2:0 SCI IRQ Select (SCI_IRQ_SEL) — R/W.
Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI must be routed
to IRQ9–11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other
PCI interrupts. If using the APIC, the SCI can also be mapped to IRQ20–23, and can be shared with
other interrupts.
When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be programmed for
active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC
should be programmed for active-low reception.
Bit Description
Bits SCI Map
000b IRQ9
001b IRQ10
010b IRQ11
011b Reserved
100b IRQ20 (Only available if APIC enabled)
101b IRQ21 (Only available if APIC enabled)
110b IRQ22 (Only available if APIC enabled)
111b IRQ23 (Only available if APIC enabled)
Bit Description
31:16 Reserved. Always 0.
15:7 Base Address (BA) — R/W. Provides the 128 bytes of I/O space for GPIO.
6:1 Reserved. Always 0.
0 RO. Hardwired to 1 to indicate I/O space.
Bit Description
7:5 Reserved
4 GPIO Enable (EN) — R/W. This bit enables/disables decode of the I/O range pointed to by the GPIO
Base Address register (D31:F0:48h) and enables the GPIO function.
0 = Disable.
1 = Enable.
3:1 Reserved