Datasheet

LPC Interface Bridge Registers (D31:F0)
244 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0)
Offset Address: 2Ch–2Fh Attribute: R/WO
Default Value: 00000000h Size: 32 bits
This register is initialized to logic 0 by the assertion of PLTRST#. This register can be
written only once after PLTRST# de-assertion.
7.1.12 CAPP—Capability List Pointer Register (LPC I/F—D31:F0)
Offset Address: 34h Attribute: RO
Default Value: E0h Size: 8 bits
7.1.13 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)
Offset Address: 40h–43h Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Lockable: No Usage: ACPI, Legacy
Power Well: Core
Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These
registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries.
7.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)
Offset Address: 44h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Usage: ACPI, Legacy
Power Well: Core
Bit Description
31:16 Subsystem ID (SSID) — R/WO. This is written by BIOS. No hardware action taken on this value.
15:0 Subsystem Vendor ID (SSVID) — R/WO. This is written by BIOS. No hardware action taken on
this value.
Bit Description
7:0 Capability Pointer (CP) — RO. Indicates the offset of the first Capability Item.
Bit Description
31:16 Reserved
15:7 Base Address — R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and TCO logic.
This is placed on a 128-byte boundary.
6:1 Reserved
0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate I/O space.
Bit Description
7 ACPI Enable (ACPI_EN) — R/W.
0 = Disable.
1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the ACPI power
management function is enabled. The APM power management ranges (B2/B3h) are always
enabled and are not affected by this bit.
6:3 Reserved