Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 243
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.5 RID—Revision Identification Register (LPC I/F—D31:F0)
Offset Address: 08h Attribute: R/WO
Default Value: See bit description Size: 8 bits
7.1.6 PI—Programming Interface Register (LPC I/F—D31:F0)
Offset Address: 09h Attribute: RO
Default Value: 00h Size: 8 bits
7.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Ah Attribute: RO
Default Value: 01h Size: 8-bit
7.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Bh Attribute: RO
Default Value: 06h Size: 8-bit
7.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0)
Offset Address: 0Dh Attribute: RO
Default Value: 00h Size: 8-bit
7.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)
Offset Address: 0Eh Attribute: RO
Default Value: 80h Size: 8-bit
Bit Description
7:0 Revision ID (RID) — R/WO. This field indicates the device specific revision identifier.
Bit Description
7:0 Programming Interface — RO.
Bit Description
7:0 Sub Class Code — RO. 8-bit value that indicates the category of bridge for the LPC bridge.
01h = PCI-to-ISA bridge.
Bit Description
7:0 Base Class Code — RO. 8-bit value that indicates the type of device for the LPC bridge.
06h = Bridge device.
Bit Description
7:3 Master Latency Count (MLC) — Reserved
2:0 Reserved
Bit Description
7 Multi-Function Device — RO. This bit is 1 to indicate a multi-function device.
6:0 Header Type — RO. This 7-bit field identifies the header layout of the configuration space.