Datasheet

LPC Interface Bridge Registers (D31:F0)
242 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)
Offset Address: 06h–07h Attribute: RO, R/WC
Default Value: 0210h Size: 16 bits
Lockable: No Power Well: Core
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
6 Parity Error Response Enable (PERE) — R/W.
0 = No action is taken when detecting a parity error.
1 = Enables Intel® Xeon® Processor D-1500 Product Family LPC bridge to respond to parity errors
detected on backbone interface.
5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.
4 Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0.
3 Special Cycle Enable (SCE) — RO. Hardwired to 0.
2 Bus Master Enable (BME) — RO. Bus Masters cannot be disabled.
1 Memory Space Enable (MSE) — RO. Memory space cannot be disabled on LPC.
0 I/O Space Enable (IOSE) — RO. I/O space cannot be disabled on LPC.
Bit Description
Bit Description
15 Detected Parity Error (DPE) — R/WC. Set when the LPC bridge detects a parity error on the
internal backbone. Set even if the PCICMD.PERE bit (D31:F0:04, bit 6) is 0.
0 = Parity Error Not detected.
1 = Parity Error detected.
14 Signaled System Error (SSE)— R/WC. Set when the LPC bridge signals a system error to the
internal SERR# logic.
13 Master Abort Status (RMA) — R/WC.
0 = Unsupported request status not received.
1 = The bridge received a completion with unsupported request status from the backbone.
12 Received Target Abort (RTA) — R/WC.
0 = Completion abort not received.
1 = Completion with completion abort received from the backbone.
11 Signaled Target Abort (STA) — R/WC.
0 = Target abort Not generated on the backbone.
1 = LPC bridge generated a completion packet with target abort status on the backbone.
10:9 DEVSEL# Timing Status (DEV_STS) — RO.
01 = Medium Timing.
8 Data Parity Error Detected (DPED) — R/WC.
0 = All conditions listed below Not met.
1 = Set when all three of the following conditions are met:
• LPC bridge receives a completion packet from the backbone from a previous request,
• Parity error has been detected (D31:F0:06, bit 15)
• PCICMD.PERE bit (D31:F0:04, bit 6) is set.
7 Fast Back to Back Capable (FBC) — RO. Hardwired to 0.
6Reserved
5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
4 Capabilities List (CLIST) — RO. Capability list exists on the LPC bridge.
3 Interrupt Status (IS) — RO. The LPC bridge does not generate interrupts.
2:0 Reserved