Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 241
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0)
Offset Address: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
Lockable: No Power Well: Core
7.1.2 DID—Device Identification Register (LPC I/F—D31:F0)
Offset Address: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bits
Lockable: No Power Well: Core
7.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
Offset Address: 04h–05h Attribute: R/W, RO
Default Value: 0007h Size: 16 bits
Lockable: No Power Well: Core
94h–97h ULKMC USB Legacy Keyboard / Mouse Control 00002000h RO, R/WC, R/
W
98h–9Bh LGMR LPC I/F Generic Memory Range 00000000h R/W
A0h–CFh Power Management (See
Section 7.8.1)
D0h–D3h BIOS_SEL1 BIOS Select 1 00112233h R/W, RO
D4h–D5h BIOS_SEL2 BIOS Select 2 4567h R/W
D8h–D9h BIOS_DEC_EN1 BIOS Decode Enable 1 FFCFh R/W, RO
DCh BIOS_CNTL BIOS Control 20h R/WLO, R/W,
RO
E0h–E1h FDCAP Feature Detection Capability ID 0009h RO
E2h FDLEN Feature Detection Capability Length 0Ch RO
E3h FDVER Feature Detection Version 10h RO
E4h–E7h FVECIDX Feature Vector Index 00000000h R/W
E8h–EBh FVECD Feature Vector Data See Description RO
F0h–F3h RCBA Root Complex Base Address 00000000h R/W
Table 7-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Attribute
Bit Description
15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
Bit Description
15:0 Device ID — RO. This is a 16-bit value assigned to Intel® Xeon® Processor D-1500 Product
Family LPC bridge..
Bit Description
15:10 Reserved
9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
8 SERR# Enable (SERR_EN) — R/W. The LPC bridge generates SERR# if this bit is set.
7 Wait Cycle Control (WCC) — RO. Hardwired to 0.