Datasheet

Introduction
24 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
1 Introduction
1.1 About This Manual
This document is intended for Original Equipment Manufacturers and BIOS vendors
creating products based on the Integrated Intel® Xeon® Processor D-1500 Product
Family Logic Platform Controller Hub. See Section 1.3 for definitions and supported
features).
Note: Throughout this document, Intel® Xeon® Processor D-1500 Product Family is used as
a general term and refers to all Intel® Xeon® Processor D-1500 Product Family
Integrated Logic Platform Controller Hub, unless specifically noted otherwise.
This manual assumes a working knowledge of the vocabulary and principles of PCI
Express*, USB, AHCI, SATA, SMBus, ACPI and Low Pin Count (LPC). Although some
details of these features are described within this manual, refer to the individual
industry specifications listed in Table 1- 1 for the complete details.
All PCI buses, devices and functions in this manual are abbreviated using the following
nomenclature; Bus:Device:Function. This manual abbreviates buses as Bn, devices as
Dn and functions as Fn. For example Device 31 Function 0 is abbreviated as D31:F0,
Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will
not be used, and can be considered to be Bus 0.
Table 1-1. Industry Specifications (Sheet 1 of 2)
Specification Location
PCI Express* Base Specification, Revision 2.0 http://www.pcisig.com/specifications
Low Pin Count Interface Specification, Revision 1.1 (LPC) http://developer.intel.com/design/chipsets/industry/lpc.htm
System Management Bus Specification, Version 2.0 (SMBus) http://www.smbus.org/specs/
PCI Local Bus Specification, Revision 2.3 (PCI) http://www.pcisig.com/specifications
PCI Power Management Specification, Revision 1.2 http://www.pcisig.com/specifications
Universal Serial Bus Specification (USB), Revision 2.0 http://www.usb.org/developers/docs
Advanced Configuration and Power Interface, Version 4.0a
(ACPI)
http://www.acpi.info/spec.htm
Enhanced Host Controller Interface Specification for
Universal Serial Bus, Revision 1.0 (EHCI)
http://developer.intel.com/technology/usb/ehcispec.htm
eXtensible Host Controller Interface for Universal Serial Bus
(xHCI), Revision 1.0
http://www.intel.com/technology/usb/xhcispec.htm
Serial ATA Specification, Revision 3.0 http://www.serialata.org/
Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0 http://www.serialata.org
Serial ATA II Cables and Connectors Volume 2 Gold http://www.serialata.org
Alert Standard Format Specification, Version 1.03 http://www.dmtf.org/standards/asf
IEEE 802.3 Fast Ethernet http://standards.ieee.org/getieee802/
AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) http://T13.org (T13 1410D)
IA-PC HPET (High Precision Event Timers) Specification,
Revision 1,0a
http://www.intel.com/hardwaredesign/hpetspec_1.pdf
Trusted Platform Module (TPM) Specification 1.3
Note: TPM over SPI supports 8 bytes transactions max.
http://www.trustedcomputinggroup.org/specs/TPM